 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
DS90CF581 数据表(PDF) 4 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
DS90CF581 数据表(HTML) 4 Page - National Semiconductor (TI) |
|
|
4 / 10 page  Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units LLHT LVDS Low-to-High Transition Time ( Figure 3) 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time ( Figure 3) 0.75 1.5 ns TCIT TxCLK IN Transition Time ( Figure 4)8 ns TCCS TxOUT Channel-to-Channel Skew (Note 6) ( Figure 5) 350 ps TPPos0 Transmitter Output Pulse Position for Bit 0 ( Figure 11)f = 20 MHz −200 150 350 ps TPPos1 Transmitter Output Pulse Position for Bit 1 6.3 7.2 7.5 ns TPPos2 Transmitter Output Pulse Position for Bit 2 12.8 13.6 14.6 ns TPPos3 Transmitter Output Pulse Position for Bit 3 20 20.8 21.5 ns TPPos4 Transmitter Output Pulse Position for Bit 4 27.2 28 28.5 ns TPPos5 Transmitter Output Pulse Position for Bit 5 34.5 35.2 35.6 ns TPPos6 Transmitter Output Pulse Position for Bit 6 42.2 42.6 42.9 ns TPPos0 Transmitter Output Pulse Position for Bit 0 ( Figure 11)f = 40 MHz −100 100 300 ps TPPos1 Transmitter Output Pulse Position for Bit 1 2.9 3.3 3.9 ns TPPos2 Transmitter Output Pulse Position for Bit 2 6.1 6.6 7.1 ns TPPos3 Transmitter Output Pulse Position for Bit 3 9.7 10.2 10.7 ns TPPos4 Transmitter Output Pulse Position for Bit 4 13 13.5 14.1 ns TPPos5 Transmitter Output Pulse Position for Bit 5 17 17.4 17.8 ns TPPos6 Transmitter Output Pulse Position for Bit 6 20.3 20.8 21.4 ns TCIP TxCLK IN Period ( Figure 6) 25 T 50 ns TCIH TxCLK IN High Time ( Figure 6) 0.35T 0.5T 0.65T ns TCIL TxCLK IN Low Time ( Figure 6) 0.35T 0.5T 0.65T ns TSTC TxIN Setup to TxCLK IN ( Figure 6)f = 20 MHz 14 ns f = 40 MHz 8 ns THTC TxIN Hold to TxCLK IN ( Figure 6) 2.5 2 ns TCCD TxCLK IN to TxCLK OUT Delay @ 25˚C, V CC = 5.0V (Figure 7) 5 9.7 ns TPLLS Transmitter Phase Lock Loop Set ( Figure 8)10 ms TPDD Transmitter Powerdown Delay ( Figure 10) 100 ns Note 6: This limit based on bench characterization. AC Timing Diagrams DS012486-15 FIGURE 1. “WORST CASE” Test Pattern www.national.com 4 |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
