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CS5509-AS 数据表(PDF) 4 Page - Cirrus Logic

部件名 CS5509-AS
功能描述  SINGLE SUPPLY 16BIT A/D CONVERTER
PDF  23 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS5509-AS 数据表(HTML) 4 Page - Cirrus Logic

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CS5509
4
DS125F2
Notes: 10. Specidified using 10% and 90% points on waveform of interest.
11. An internal power-on-reset is activated whenever power is applied to the device.
12. Oscillator start-up time varies with the crystal parameters. This specification does not apply when using
an external clock source.
13. The wake-up period begins once the oscillator starts; or when using an external fclk, after the power-on
reset time elapses.
14. Calibration can also be initiated by pulsing CAL high while CONV=1.
15. Conversion time will be 1622/fclk if CONV remains high continuously.
5V SWITCHING CHARACTERISTICS (T
A = 25 °C; VA+, VD+ = 5V ±10%; Input Levels: Logic 0 =
0V, Logic 1 = VD+; CL = 50 pF) (Note 2)
Parameter
Symbol
Min
Typ
Max
Unit
Master Clock Frequency
Internal Oscillator
External Clock
XIN
fclk
30.0
30
32.768
-
53.0
330
kHz
kHz
Master Clock Duty Cycle
40
-
60
%
Rise Times
Any Digital Input
(Note 10)
Any Digital Output
trise
-
-
-
50
1.0
-
µs
ns
Fall Time
Any Digital Input
(Note 10)
Any Digital Output
tfall
-
-
-
20
1.0
-
µs
ns
Start-Up
Power-On Reset Period
(Note 11)
tres
-10-
ms
Oscillator Start-up Time
XTAL = 32.768 kHz (Note 12)
tosu
-500-
ms
Wake-up Period
(Note 13)
twup
-
1800/fclk
-s
Calibration
CONV Pulse Width (CAL = 1)
(Note 14)
tccw
100
-
-
ns
CONV and CAL High to Start of Calibration
tscl
--
2/fclk+200
ns
Start of Calibration to End of Calibration
tcal
-
3246/fclk
-s
Conversion
CONV Pulse Width
tcpw
100
-
-
ns
CONV High to Start of Conversion
tscn
--
2/fclk+200
ns
Set Up Time
BP/UP stable prior to DRDY falling
tbus
82/fclk
--
s
Hold Time
BP/UP stable after DRDY falls
tbuh
0-
-
ns
Start of Conversion to End of Conversion
(Note 15)
tcon
-
1624/fclk
-s



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