CS5525 CS5526

DS202F3

17

The offset and gain calibration steps each take one

conversion cycle to complete. At the end of the cal-

ibration step, the calibration control bits will be set

back to logic 0, and the DF (Done Flag) bit will be

set to a logic 1. For the combination self-calibra-

tion (CC2-CC0= 011; offset followed by gain), the

calibration will take two conversion cycles to com-

plete and will set the DF bit after the gain calibra-

tion is completed. The DF bit will be cleared any

time the data register, the offset register, the gain

register, or the setup register is read. Reading the

configuration register alone will not clear the DF

bit.

Self Calibration

The CS5525/26 offer both self offset and self gain

calibrations. For the self-calibration of offset in the

25 mV, 55 mV, and 100 mv ranges, the converter

internally ties the inputs of the instrumentation am-

plifier together and routes them to the AIN- pin as

shown in Figure 10. For proper self-calibration of

offset to occur in the 25 mV, 55 mV, and 100 mV

ranges, the AIN- pin must be at the proper com-

mon-mode-voltage (i.e. AIN- = 0V, NBV must be

between -1.8 V to -2.5 V). For self-calibration of

offset in the 1.0 V, 2.5 V, and 5 V ranges, the inputs

of the modulator are connected together and then

routed to the VREF- pin as shown in Figure 11.

For self-calibration of gain, the differential inputs

of the modulator are connected to VREF+ and

Table 3.

Table 4. Offset and Gain Registers

Offset Register

Offset and data word bits align by MSB (bit MSB-4 of offset register changes bit MSB-4 of data)

Gain Register

MSB

LSB

Register

Sign

Reset (R)

0

0

0

0

0

0

0

00

00

0

MSB

LSB

Register

Reset (R)

1

0

0

0

0

0

00

00

00

AIN +

AIN -

S1

OP E N

S2

CL O SE D

+

-

X20

+

-

Figure 10. Self Calibration of Offset (Low Ranges).

AIN +

AIN -

S1

O PEN

+

-

X20

+

-

S2

O PEN

S4

CLO S ED

VR EF-

Figure 11. Self Calibration of Offset (High Ranges).