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ES1022SI 数据表(PDF) 9 Page - Altera Corporation

部件名 ES1022SI
功能描述  Adjustable Quad Sequencer
PDF  14 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

ES1022SI 数据表(HTML) 9 Page - Altera Corporation

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Page 9
Enpirion Power Datasheet ES1022SI Adjustable Quad Sequencer
May 2014
Altera Corporation
Applications Usage
Using the EVB-ES1022SI Platform
The EVB-ES1022SI platform is the primary evaluation board for this family of sequencers. See Figure 15 for
photograph and schematic. The evaluation board is shipped with an ES1022SI mounted in the left position and with
the other device variants loose packed. In the following discussion, test points names are bold on initial occurrence for
identification.
The VIN test point is the chip bias and can be biased from 3.3V to 24V. The VHI test point is for the EN and FAULT
pull-up voltage which are limited to a maximum of 24V independent of VIN. The UV/OV resistor divider is set so that
a nominal 12V on the VMONITOR test point is compliant and with a rising OV set at 13.2V and a falling UV set at
10.7V. These three test points (VIN,VHI and VMONITOR) are brought out separately for maximum flexibility in
evaluation.
VMONITOR ramping up and down through the UV and OV levels will result in the FAULT output signaling the out
of bound conditions by being released to pull high to the VHI voltage as shown in Figures 6 and 7.
Once the voltage monitoring FAULT is resolved and where applicable, the SEQ_EN is satisfied, sequencing of the
EN_X outputs begins. When sequence enabled the EN_A, EN_B, EN_C and lastly EN_D are asserted in that order and
when SEQ_EN is disabled the order is reversed. See Figures 8 and 9 demonstrating the sequenced enabling and
disabling of the EN outputs. The timing between EN outputs is set by the resistor values on the TDLY_AB, TDLY_BC,
TDLY_CD pins as shown. Figure 10 illustrates the timing from either SEQ_EN and/or VMONITOR being valid to
EN_A being asserted with a 10nF TIME capacitor. Figure 11 shows that EN_X outputs are pulled low even before VIN
= 1V. This is critical to ensure that a false EN is not signaled. Figure 12 shows the time from SEQ_EN transition with
the voltage ramping across the TIME capacitor to TIME Vth being met. This results in the immediate pull down of the
TIME pin and simultaneous EN_A enabling.
FIGURE 6. VMONITOR RISING TO FAULT
FIGURE 7. VMONITOR FALLING TO FAULT
FAULT OUTPUT
VMON RISING
VMON > UV
VMON > OV
LEVEL
LEVEL
VMON FALLING
VMON > OV
VMON > UV
LEVEL
LEVEL
FAULT OUTPUT
10037
May 28, 2014
Rev A



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