MOTOROLA

MPC185 Security Processor Technical Summary

3

PowerPC-architectured processor and memory controller. The ability of the MPC185 to be a master on the

60x bus allows the co-processor to offload the data movement bottleneck normally associated with slave

devices.

The host processor accesses the MPC185 through its device drivers using system memory for data storage.

The MPC185 resides in the memory map of the processor, therefore when an application requires

cryptographic functions, it simply creates descriptors for the MPC185 which define the cryptographic

function to be performed and the location of the data. The MPC185’s 60x-mastering capability permits the

host processor to set up a crypto-channel with a few short register writes, leaving the MPC185 to perform

reads and writes on system memory to complete the required task.

Figure 4-1. MPC185 Connected to PowerQuicc II 60xBus

Figure 4-2 shows a configuration with the MPC185 communicating with the host processor via a PCI

bridge, such as the MPC107.

Figure 4-2. MPC185 Connected to host CPU via a Bridge

MPC82xx

MPC185

EEPROM

Main

I/O or Network

Interface

PCI or Local Bus

60x Bus

Memory

PCI Local Bus

60x Bus

Main

Memory

MPC7xx, MPC74xx

MPC107

PCI Bridge

Network

Interface Card

MPC185

PCI

Application

Network

Interface Card

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com