MSC1210 datasheet(21/83 Pages) TI

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MSC1210

SBAS203F − MARCH 2002 − REVISED NOVEMBER 2004

www.ti.com

CLK

instr_cycle

cpu_cycle

n+ 1

n + 2

Figure 9. Instruction Timing Cycle

ENHANCED 8051 CORE

All instructions in the MSC1210 family perform exactly the

same functions as they would in a standard 8051. The

effect on bits, flags, and registers is the same. However,

the timing is different. The MSC1210 family utilizes an

efficient 8051 core which results in an improved instruction

execution speed of between 1.5 and 3 times faster than the

original core for the same external clock speed (4 clock

cycles per instruction versus 12 clock cycles per

instruction, as shown in Figure 9). The internal system

clock is equal to the external oscillator frequency. This

translates into an effective throughput improvement of

more than 2.5 times, using the same code and same

external clock speed.

Therefore, a device frequency of 33MHz for the

MSC1210Yx actually performs at an equivalent execution

speed of 82.5MHz compared to the standard 8051 core.

This allows the user to run the device at slower external

clock speeds which reduces system noise and power

consumption, but provides greater throughput. This

performance difference can be seen in Figure 10. The

timing of software loops will be faster with the MSC1210.

However, the timer/counter operation of the MSC1210

may be maintained at 12 clocks per increment or optionally

run at 4 clocks per increment.

The MSC1210 also provides dual data pointers (DPTRs)

to speed block Data Memory moves.

Additionally, it can stretch the number of memory cycles to

access external Data Memory from between two and nine

instruction cycles in order to accommodate different

speeds of memory or devices, as shown in Table 1. The

MSC1210 provides an external memory interface with a

16-bit address bus (P0 and P2). The 16-bit address bus

makes it necessary to multiplex the low address byte

through the P0 port. To enhance P0 and P2 for high-speed

memory access, hardware configuration control is

provided

configure

the

ports

for

external

memory/peripheral interface or general-purpose I/O.

Furthermore, improvements were made to peripheral

features that off-load processing from the core, and the

user, to further improve efficiency. For instance, 32-bit

accumulation can be done through the summation register

to significantly reduce the processing overhead for the

multiple byte data from the ADC or other sources. This

allows for 32-bit addition and shifting to be accomplished

in a few instruction cycles, compared to hundreds of

instruction cycles through a software implementation.

Table 1. Memory Cycle Stretching. Stretching of

MOVX timing as defined by MD2, MD1, and MD0

bits in CKCON register (address 8Eh).

CKCON

(8Eh)

MD2:MD0

INSTRUCTION

CYCLES

(for MOVX)

RD or WR

STROBE WIDTH

(SYS CLKs)

RD or WR

STROBE WIDTH

(

ms) AT 12MHz

000

0.167

001

3 (default)

0.333

010

0.667

011

1.000

100

1.333

101

1.667

110

2.000

111

2.333

ALE

PSEN

AD0−AD7

PORT 2

ALE

PSEN

AD0−AD7

PORT 2

CLK

Single−Byte, Single−Cycle

Instruction

12 Cycles

4 Cycles

Single−Byte, Single−Cycle

Figure 10. Comparison of MSC1210 Timing to

Standard 8051 Timing

MSC1210 数据表(PDF) 21 Page - Texas Instruments

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