NCP500

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14

APPLICATIONS INFORMATION

The NCP500 series regulators are protected with internal

thermal shutdown and internal current limit. A typical

application circuit is shown in Figure 27.

Input Decoupling (C1)

A 1.0

mF capacitor either ceramic or tantalum is

recommended and should be connected close to the NCP500

package. Higher values and lower ESR will improve the

overall line transient response.

Output Decoupling (C2)

The NCP500 is a stable component and does not require

a minimum Equivalent Series Resistance (ESR) or a

minimum output current. The minimum decoupling value is

1.0

mF and can be augmented to fulfill stringent load

transient requirements. The regulator accepts ceramic chip

capacitors as well as tantalum devices. Larger values

improve noise rejection and load regulation transient

response. Figure 29 shows the stability region for a range of

operating conditions and ESR values.

Noise Decoupling

The NCP500 is a low noise regulator without the need of

an external bypass capacitor. It typically reaches a noise level

of 50

mVRMS overall noise between 10 Hz and 100 kHz. The

classical bypass capacitor impacts the start up phase of

standard LDOs. However, thanks to its low noise

architecture, the NCP500 operates without a bypass element

and thus offers a typical 20

ms start up phase.

Enable Operation

The enable pin will turn on or off the regulator. These

limits of threshold are covered in the electrical specification

section of this data sheet. The turn−on/turn−off transient

voltage being supplied to the enable pin should exceed a

slew rate of 10 mV/

ms to ensure correct operation. If the

enable is not to be used then the pin should be connected

Thermal

As power across the NCP500 increases, it might become

necessary to provide some thermal relief. The maximum

power dissipation supported by the device is dependent

upon board design and layout. Mounting pad configuration

on the PCB, the board material, and the ambient temperature

effect the rate of junction temperature rise for the part. This

is stating that when the NCP500 has good thermal

conductivity through the PCB, the junction temperature will

be relatively low with high power dissipation applications.

The maximum dissipation the package can handle is

given by:

PD

+

TJ(max) *TA

R

qJA

NCP500 can dissipate up to 400 mW @ 25

°C.

The power dissipated by the NCP500 can be calculated

from the following equation:

Ptot + [Vin *Ignd (Iout)] ) [Vin * Vout] *Iout

or

VinMAX +

Ptot ) Vout * Iout

Ignd ) Iout

If a 150 mA output current is needed the ground current

is extracted from the data sheet curves: 200

mA @ 150 mA.

For a NCP500SN18T1 (1.8 V), the maximum input voltage

will then be 4.4 V, good for a 1 Cell Li−ion battery.

Hints

When the impedance of these lines is high, there is a chance

to pick up noise or cause the regulator to malfunction.

Set external components, especially the output capacitor,

as close as possible to the circuit, and make leads as short

as possible.

Package Placement

QFN packages can be placed using standard pick and

place equipment with an accuracy of

"0.05 mm.

Component pick and place systems are composed of a vision

system that recognizes and positions the component and a

mechanical system which physically performs the pick and

place operation. Two commonly used types of vision

systems are: (1) a vision system that locates a package

silhouette and (2) a vision system that locates individual

bumps on the interconnect pattern. The latter type renders

more accurate place but tends to be more expensive and time

consuming. Both methods are acceptable since the parts

align due to a self−centering feature of the QFN solder joint

during solder re−flow.

Solder Paste

Type 3 or Type 4 solder paste is acceptable.

Re−flow and Cleaning

The QFN may be assembled using standard IR/IR

convection SMT re−flow processes without any special

considerations. As with other packages, the thermal profile

for specific board locations must be determined. Nitrogen

purge is recommended during solder for no−clean fluxes.

The QFN is qualified for up to three re−flow cycles at 235

°C

peak (J−STD−020). The actual temperature of the QFN is a

function of: