M68AF031AM70N datasheet(10/22 Pages) STMICROELECTRONICS

10 / 22 page

M68AF031A

10/22

OPERATION

The M68AF031A has a Chip Enable power down

feature which invokes an automatic standby mode

whenever Chip Enable is de-asserted (E = High).

An Output Enable (G) signal provides a high

speed tri-state control, allowing fast read/write cy-

cles to be achieved with the common I/O data bus.

Operational modes are determined by device con-

trol inputs W and E, as summarized in the Operat-

ing Modes table (see Table 6., Operating Modes).

Table 6. Operating Modes

Note: 1. X = VIH or VIL.

Read Mode

The M68AF031A is in the Read mode whenever

Write Enable (W) is High with Output Enable (G)

Low, and Chip Enable (E) is asserted. This pro-

vides access to data of the 262,144 locations in

the static memory array, specified by the 15 ad-

dress inputs. Valid data will be available at the

eight output pins within tAVQV after the last stable

address, providing G is Low and E is Low. If Chip

Enable or Output Enable access times are not

met, data access will be measured from the limit-

ing parameter (tELQV or tGLQV) rather than the ad-

dress. Data out may be indeterminate at tELQX and

tGLQX but data lines will always be valid at tAVQV.

Figure 10. Address Controlled, Read Mode AC Waveforms

Note: E = Low, G = Low, W = High.

Operation

DQ0-DQ7

Power

Deselected

VIH

Hi-Z

Standby (ISB)

Read

VIL

VIH

VIL

Data Output

Active (ICC)

Write

VIL

Data Input

Active (ICC)

Output Disabled

VIL

VIH

Hi-Z

Active (ICC)

AI05939

tAVAV

tAVQV

tAXQX

A0-A14

DQ0-DQ7

VALID

DATA VALID

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