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PCM1602 数据表(PDF) 13 Page - Texas Instruments |
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PCM1602 数据表(HTML) 13 Page - Texas Instruments |
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13 / 29 page ![]() PCM1602 13 SBAS163 REGISTER WRITE OPERATION All Write operations for the serial control port use 16-bit data words. Figure 6 shows the control data word format. The most significant bit is the Read/Write (R/W) bit. When set to “0”, this bit indicates a Write operation. There are seven bits, labeled IDX[6:0], that set the register index (or address) for the Write operation. The least significant eight bits, D[7:0], contain the data to be written to the register specified by IDX[6:0]. Figure 7 shows the functional timing diagram for writing the serial control port. ML is held at a logic “1” state until a register needs to be written. To start the register write cycle, ML is set to logic “0”. Sixteen clocks are then provided on MC, corresponding to the 16-bits of the control data word on MDI. After the sixteenth clock cycle has completed, ML is set to logic “1” to latch the data into the indexed mode control register. SINGLE REGISTER READ OPERATION Read operations utilize the 16-bit control word format shown in Figure 6. For Read operations, the R/W bit is set to “1”. Read operations ignore the index bits, IDX[6:0], of the control data word. Instead, the REG[6:0] bits in Control Register 11 are used to set the index of the register that is to be read during the Read operation. Bits IDX[6:0] should be set to 00H for Read operations. FIGURE 5. Audio Interface Timing. SYMBOL PARAMETER MIN MAX UNITS tBCY BCK Pulse Cycle Time 32, 48, or 64fS(1) tBCH BCK High Level Time 35 ns tBCL BCK Low Level Time 35 ns tBL BCK Rising Edge to LRCK Edge 10 ns tLB LRCK Falling Edge to BCK Rising Edge 10 ns tDS DATA Set Up Time 10 ns tDH DATA Hold Time 10 ns NOTE: (1) fS is the sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.) LRCK BCK DATA1,DATA2, DATA3, DATA4 50% of V DD 50% of V DD 50% of V DD t BCH t BCL t LB t BL t DS t DH t BCY FIGURE 6. Control Data Word Format for MDI. IDX5 IDX6 R/W IDX4 IDX2 IDX3 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0 MSB Register Index (or Address) Read/Write Operation 0 = Write Operation 1 = Read Operation (register index is ignored) Register Data LSB FIGURE 7. Write Operation Timing. R/W D7 D6 D5 D4 D3 D2 RW IDX6 D1 D0 X XX IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 ML MC MDI |
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