NCP4353, NCP4354

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10

APPLICATION INFORMATION

A typical application circuit for NCP435x series is shown

in Figure 28, done with an imaginary IC with all features in

one. Pin functions are available in pin description table.

Simplified typical application circuit for NCP4353B that

shows only available features in this IC is shown in

Figure 27. Figure 29 shows possible connection of the

NCP4353B to flyback primary controller.

IC will be derived in multiple versions with different

features for each of them.

Power Supply

The NCP435x is designed to operate from a single supply

up to 36 V. It starts to operate when VCC voltage reaches

can be supplied by direct connection to the VOUT voltage

of the power supply. It is highly recommended to add a RC

filter (R1 and C3) in series from VOUT to VCC pin to reduce

voltage spikes and drops that are produced at the converter’s

output capacitors. Recommended values for this filter are

220

W and 1 mF.

Voltage Regulation Path

The output voltage is detected on the VSNS pin by the R4,

R5 and R6 voltage divider. This voltage is compared with

the internal precise voltage reference. The voltage

amplifier. The amplifier output current is connected to the

FBC or DRIVE pin. The compensation network is also

connected to this pin to provide frequency compensation for

the voltage regulation path. This FBC (DRIVE) pin drives

regulation optocoupler that provides regulation of primary

side. The optocoupler is supplied via direct connection to

VOUT line through resistor R2.

Regulation information is transferred through the

optocoupler to the primary side controller where its FB pin

is usually pulled down to reduce energy transferred to

secondary output.

The VSNS voltage divider is shared with VMIN voltage

divider. The shared voltage divider can be connected in two

ways as shown in Figure 26. The divider type is selected

condition of Equation 1 is true, divider type 1 should be

used.

V

V

OUT

V

REFM

V

REF

(eq. 1)

Output voltage for divider type 1 can be computed by

Equation 2

V

R4

) R5 ) R6

R5

) R6

(eq. 2)

and for type 2 by Equation 3.

V

R4

) R5 ) R6

R6

(eq. 3)

R7

VSNS

VMIN

R4

R5

R6

VOUT

R7

VSNS

VMIN

R4

R5

R6

VOUT

TYPE 1

TYPE 2

Figure 26. Shared Dividers Type

Current Regulation Path (A versions only)

The output current is sensed by the shunt resistor R12 in

series with the load. Voltage drop on R12 is compared with

internal

precise

voltage

reference

transconductance amplifier input.

of

amplifier,

connected

to

FBC

or

DRIVE

pin.

Compensation network is connected between this pin and

ISNS input to provide frequency compensation for current

regulation path. Resistor R13 separates compensation

network from sense resistor. Compensation network works

into low impedance without this resistor that significantly

decreases compensation network impact.

Current regulation point is set to current given by

Equation 4.

I

V

REFC

R12

(eq. 4)

OFF Mode Detection

OFF mode operation is advantageous for ultra low or zero

output current condition. The very long off time and the ultra

low power mode of the whole regulation system greatly

reduces the overall consumption.

The output voltage is varying between nominal and

minimal in OFF mode. When output voltage decreases

below set (except NCP4353A) minimum level, primary

controller is switched on until output capacitor C1 is charged

again to the nominal voltage.

The OFF mode detection is based on comparison of output

voltage and voltage loaded with fixed resistances (D2, C2,

R8 and R9). Figure 30 shows detection waveforms. When

output voltage is loaded with very low current, primary

controller goes into skip mode (primary controller stops

switching for some time). While output capacitor C1 is

discharged very slowly (no load condition), the capacitor C2