FAILURE DETECTION

TABLE 4. FPD85310 Failure Detection

Mode

No

Clock

No

VSYNC

No

HSYNC

No

ENAB

Fix Vertical/Horizontal

(1)

(2)

(3)

—

Fix Vertical/ENAB Horizontal

(1)

(2)

—

(4)

ENAB Only Mode

(1)

—

—

(5)

(1) Wait (

∼2) ms then output 2048 pixels/line and 2047 lines/frame. No esp/osp. No eclk/oclk.

(2) Wait (

∼2) ms then output input line time and 2047 lines/frame. With esp/osp. With eclk/oclk.

(3) Wait (

∼2) ms then output 2048 pixels/line and input frame time. With esp/osp. With eclk/oclk.

(4) Wait (

∼2) ms then output 2048 pixels/line and input frame time. No esp/osp. With eclk/oclk.

(5) Wait (

∼2) ms then output 2048 pixels/line and 2047 lines/frames. No esp/osp. With eclk/oclk.

∼25 MHz.

*GPO control outputs are generated per programmed values.

DS101086-11

FIGURE 17. Delay Circuit for Stable RSTZ

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