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SAF7118EH 数据表(PDF) 9 Page - NXP Semiconductors |
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SAF7118EH 数据表(HTML) 9 Page - NXP Semiconductors |
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9 / 173 page  2004 Jul 22 9 Philips Semiconductors Product specification Multistandard video decoder with adaptive comb filter and component video input SAF7118 VDDD5 73 M11 P digital supply voltage 5 (peripheral cells) ASCLK 74 N11 O audio serial clock output ALRCLK 75 P12 O/st/pd audio left/right clock output; can be strapped to supply via a 3.3 k Ω resistor to indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down) has been replaced by a 32.110 MHz crystal (ALRCLK = 1); notes 5 and 7 AMXCLK 76 M12 I audio master external clock input ITRDY 77 N12 I/pu target ready input for image port data DNC0 78 P13 I/pu do not connect, reserved for future extensions and for testing: scan input DNC16 79 N13 NC do not connect, reserved for future extensions and for testing DNC17 80 N14 NC do not connect, reserved for future extensions and for testing DNC19 81 − NC do not connect, reserved for future extensions and for testing DNC20 82 − NC do not connect, reserved for future extensions and for testing FSW 83 M13 I/pd fast switch (blanking) with internal pull-down inserts component inputs into CVBS signal ICLK 84 M14 I/O clock output signal for image port, or optional asynchronous back-end clock input IDQ 85 L13 O output data qualifier for image port (optional: gated clock output) ITRI 86 L12 I/(O) image port output control signal, affects all input port pins inclusive ICLK, enable and active polarity is under software control (bits IPE in subaddress 87H); output path used for testing: scan output IGP0 87 L14 O general purpose output signal 0; image port (controlled by subaddresses 84H and 85H) VSSD5 88 L11 P digital ground 5 (peripheral cells) IGP1 89 K13 O general purpose output signal 1; image port (controlled by subaddresses 84H and 85H) IGPV 90 K14 O multi purpose vertical reference output signal; image port (controlled by subaddresses 84H and 85H) IGPH 91 K12 O multi purpose horizontal reference output signal; image port (controlled by subaddresses 84H and 85H) IPD7 92 K11 O MSB of image port data output IPD6 93 J13 O MSB − 1 of image port data output IPD5 94 J14 O MSB − 2 of image port data output VDDD6 95 J12 P digital supply voltage 6 (core) VSSD6 96 J11 P digital ground 6 (core) IPD4 97 H13 O MSB − 3 of image port data output IPD3 98 H14 O MSB − 4 of image port data output IPD2 99 H11 O MSB − 5 of image port data output IPD1 100 G12 O MSB − 6 of image port data output VDDD7 101 H12 P digital supply voltage 7 (peripheral cells) IPD0 102 G14 O LSB of image port data output SYMBOL PIN TYPE(1) DESCRIPTION QFP160 HBGA156 |
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