I²C Bus Selection

STV6413

20/28

Note: 1 The Interrupt Flag will be cleared when this register is read. To prepare for a new interrupt, a “1”

must be re-written in the IT Enable bit (Reg. 04, d7).

3.2

Power-on Reset — Bus Register Initial Conditions

Non-significant bits (X) are pre-set to “0”.

Table 10: Output Signals (Read Mode)

Reg.

Add.

Description

Bits

Data

Comments

d7

d6

d5

d4

d3

d2

d1

d0

Slow Blanking TV SCART

2

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

0

1

1

1

0

1

Input < 2 V

Input 16/9 format

Input 4/3 format

Slow Blanking VCR SCART

2

X

X

X

X

X

X

X

X

X

X

X

X

0

1

1

1

0

1

X

X

X

X

X

X

Input < 2 V

Input 16/9 format

Input 4/3 format

Interrupt Flag

1

X

X

X

X

X

X

0

1

X

X

X

X

X

X

X

X

No change since read

One change has been

detected (refer to Note 1)

Reg.

Add.

Data

Comments

d7

d6

d5

d4

d3

d2

d1

d0

00h

0

0

0000

00

Audio TV and Cinch outputs are in Stereo Mode, 0 dB Gain

Adjustment.

01h

0

0

0000

00

TV, Cinch and VCR audio outputs are muted. VCR output is in Stereo

Mode.

02h

0

0

0000

00

VCR, TV video outputs are muted.

03h

0

0

0000

00

Fast Blanking is forced to ‘0’. RGB outputs are muted and in high

impedance.

04h

0

0

0000

00

C_GATE is high. C_VCR is high impedance.

05h

0

0

0000

00

Encoder and VCR R/Csub Bottom Level Clamp, RGB outputs 6 dB

Gain, and Slow Blanking parts are in read mode.

06h

0

0

0000

00

All internal blocks are ON.