STV9118 datasheet(29/46 Pages) STMICROELECTRONICS

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STV9118

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generated from the output vertical deflection drive

waveform, they both track with real vertical ampli-

tude and position (including breathing compensa-

tion), thus being fixed on the screen. Refer to I2C

BUS CONTROL REGISTER MAP on page 21 for

details on I2C bus controls.

Figure 7. Horizontal timing diagram

Figure 8. HFly input configuration

10.3.6 - Output Section

The H-drive signal is inhibited (high level) during

flyback pulse, and also when VCC is too low, when

X-ray protection is activated (XRayAlarm I2C bus

flag set to 1) and when I2C bus bit HBOutEn is set

to 0 (default position).

The duty cycle of the H-drive signal is controlled

via I2C bus register

HDUTY. This is overruled dur-

ing soft-start and soft-stop procedures (see sub

chapter Soft-start and soft-stop on H-drive on

page 29 and Figure 10).

The PLL2 is followed by a rapid phase shifting

which accepts the signal from H-moiré canceller

(see sub chapter Horizontal moiré cancellation on

page 29)

The output stage consists of a NPN bipolar tran-

sistor, the collector of which is routed to HOut pin

(see Figure 9).

Figure 9. HOut configuration

Non-conductive state of HOT (Horizontal Output

Transistor) must correspond to non-conductive

state of the device output transistor.

10.3.7 - Soft-start and soft-stop on H-drive

The soft-start and soft-stop procedure is carried

out at each switch-on or switch-off of the H-drive

signal, either via HBOutEn I2C bus bit or after re-

set of XRayAlarm I2C bus flag, to protect external

power components. By its second function, the ex-

ternal capacitor on pin HPosF is used to time out

this procedure, during which the duty cycle of H-

drive signal starts at its maximum (“tHoff/TH for soft

start/stop” in electrical specifications) and slowly

decreases to the value determined by the control

I2C bus register

HDUTY (vice versa at soft-stop).

This is controlled by voltage on pin HPosF. See

Figure 10 and sub chapter Safety functions on

page 36.

10.3.8 - Horizontal moiré cancellation

The horizontal moiré canceller is intended to blur a

potential beat between the horizontal video pixel

period and the CRT pixel width, which causes vis-

ible moiré patterns in the picture.

On pin HMoiré, in position “External” of I2C bus bit

HMoiMode, it generates a square line-synchro-

nized waveform with amplitude adjustable through

HMOIRE I2C bus control. In position “Internal” of

I2C bus bit HMoiMode, it introduces a microscopic

indent on horizontal scan lines by injecting little

controlled phase shifts to output circuitry of the

horizontal section. Their amplitude is adjustable

through

HMOIRE I2C bus control.

Only one H-moiré, internal or external, is generat-

ed at a time.

H-flyback

PLL2

H-drive

current

VThrHFly

control

(on HOut)

tHoff

H-drive

region

H-drive

region

tph(max)

inhibited

tS: HOT storage time

H-Osc

VS(0)

7/8TH

VHOThrHi

max.

med.

min.

VHPosF

H-sync

(polarized)

REF1

tHph

min

max

HPOS

(I2C)

max.

med.

min.

PLL1 lock

(internal)

VHOThrLo

(VCO)

control

forced high

forced low

OFF

GND

~20k

Ω

HFly 12

~500

Ω

int.

ext.

int.

ext.

HOut

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