STV223X datasheet(21/86 Pages) STMICROELECTRONICS

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STV224XH/228XH/223XH - FUNCTIONAL DESCRIPTION

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– A second CVBS output (CVBSOUT2) is able to

output recombined Y+C signals.

All switches are independently controlled.

– SVHS switch, Y input is combined with CVBS 3

input. CVBS/SVHS modes can be selected ei-

ther by bus control (software selection), or by

sensing the DC voltage on the Chroma Input pin

(hardware selection). If the Chroma Input is

grounded, the CVBS mode is selected and the

bus control is not active. If the DC level of the

Chroma Input is higher than the SVHS threshold,

then the bus control for the SVHS switch is ac-

tive. Therefore, the SVHS mode can be selected

by hardware using a special SVHS connector

that includes a mechanical switch. In this type of

application, the bus control is set to SVHS mode,

and the CVBS mode is selected by grounding the

Chroma Input pin.

3.2 DEFLECTION PART

3.2.1 Synchronization Separator

– Fully-integrated synchronization separator with a

low pass filter, black level alignment of the CVBS

input, and a 50% slicing level for the synchro-

nized pulse amplitude.

3.2.2 Two Phase-Locked Loops (PLL)

Auto-calibrated VCO using the chroma crystal ref-

erence. Crystal control pin X1/VAMP/CHROUT in-

dicates the crystal reference value on Pin XTAL1.

When

4.43 MHz

crystal

connected

Pin XTAL1, the output load on Pin X1/VAMP/

CHROUT must be greater than 80 k

W. When a

3.58 MHz crystal is connected to Pin XTAL1, the

output load must be less than 10 k

The first PLL locks the VCO to the video line fre-

quency and the second PLL compensates the line

transistor storage time.

Three time constants for the first PLL.

– [X,Y]: Line number referring to the internal line

counter numbering system.

The long time constant is used for normal opera-

tion.

The short time constant is automatically used dur-

ing the VCR search mode and frame retrace when

the

frame

pulse

outside

[258,264]

and

[309,314].

The very long time constant is used when there is

no video recognition (very good OSD stability).

Time constants in normal operation (automatic se-

lection of time constants):

– 50 Hz input signal:

short time constant: [306,21],

long time constant: the rest of the field.

– 60 Hz input signal:

short time constant: [0,16],

long time constant: the rest of the field.

3.2.2.1 Inhibition of the First PLL

The first PLL is inhibited from line 309 to line 4.5

(or 314) in 50 Hz mode and from line 258 to line

5.5 (or 264) in 60 Hz mode. The time constant val-

ues are chosen by means of external components.

– Possibility of forcing the short time constant dur-

ing the all frame via the bus.

– Possibility of forcing the long time constant dur-

ing the all frame via the bus.

– Possibility of forcing a very long time constant

during the all frame via the bus.

Generation of burst gate pulses and line frequency

signals from the first PLL to drive the Chroma and

Video circuits. The burst gate pulse is also sent to

the super-sandcastle generator.

3.2.3 Video Identification

The video identification status is available in the

output register of the I²C bus decoder (independ-

ent from PLL1).

3.2.4 Vertical Synchronization

Frame synchronized window:

– large window: [248,352] in AUTO mode,

[248,284] in forced 60 Hz mode, [288,352] in

forced 50 Hz mode.

– narrow window: [309,314] in 50 Hz mode,

[258,264] in 60 Hz mode.

Field frequency selection windows:

– [248,284] 60 Hz mode selection window.

– [288,352] 50 Hz mode selection window.

Frame blanking pulse adapted to standard:

– from line 309 to line 21 in 50 Hz mode,

– from line 258 to line 16 in 60 Hz mode.

3.2.5 Vertical Blanking

Long blanking mode: the end of frame blanking is

line 21 both in 50 and 60 Hz modes. This mode is

useful when the flyback time of the vertical output

stage is longer than the 60 Hz blanking time. It is

used to optimize the 50/60 Hz vertical amplifier ap-

plication due to long frame blanking.

3.2.6 Vertical Oversize Blanking

The Oversized Blanking function is controlled by

the voltage on the FBOSD pin. When the FBOSD

voltage is between the first and the second thresh-

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