The LS1012A includes a hardware

packet forwarding engine (PFE) which

offloads processing of IP packets

from the main CPU, yielding higher

performance and lower power than

pure software processing can achieve.

The PFE is capable of 2 Gbit/s IP

forwarding even with the smallest

packets, with virtually no CPU load.

COMPLETE ENABLEMENT,

RICH ECOSYSTEM

For customer evaluation, the QorIQ

LS1012A processor will be supported

by an evaluation board featuring

an integrated on-board probe for

further cost savings, along with third-

party platforms developed by NXP’s

embedded board solution partners.

optimized drivers to support peripherals

and a six-month evaluation license for

CodeWarrior development tools.

All QorIQ LS series devices are

supported by our Product Longevity

Program to ensure long-term availability,

as well as our extensive third-party

ecosystem, the largest and most

established in the communications

market. In conjunction with our expertise

and worldwide support infrastructure, the

ecosystem helps customers accelerate

their migration from both competitive

solutions and from legacy Freescale

devices, preserve investment costs and

reduce time-to-market.

QorIQ LS1012A BLOCK DIAGRAM

QorIQ LS1012A FEATURES

Core Complex

Basic Peripherals and Interconnect

Accelerators and Memory Control

Networking Elements

CoreLink™ CCI-400 Coherent Interconnect

Secure Boot

QorIQ Trust Architecture

Power Management

2 x SD 3.0/SDIO/eMMC

QSPI, 1 x SPI

2 x UART

16-bit DDR3L

Memory

Controller

128 KB

SRAM

GPIO, JTAG

Security

Engine

256 KB L2

32 KB

L1-D

32 KB

L1-I

1 x USB 3.0 + PHY

3-Lane 6 GHz SERDES

Packet Forwarding

Engine

1 x USB 2.0

Security Monitor

Document Number:

LS1012AFS REV 0

www.nxp.com/QorIQ

NXP, the NXP logo, Freescale, CodeWarrior, Layerscape, QorIQ and SMARTMOS, are trademarks of NXP B.V.

All other product or service names are the property of their respective owners. ARM, Cortex and TrustZone are

registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. CoreLink and NEON are

trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. © 2016 NXP B.V.

at 1 W typical power

ECC-protected cache memories

First 1 W typical power embedded processor featuring ARM

Cortex-A53 core with ECC protected caches and coherent

256 KB L2 for high reliability applications

Rich connectivity and peripheral

USB 3.0, SATA 3, QuadSPI, SDIO

High integration that enables support for 802.11ac modules

and high bandwidth connectivity for ASICs, 4G/LTE, SATA,

low-cost NOR Flash

Packet acceleration engine

Delivers hardware acceleration for outstanding IP forwarding

and NAS performance

Security and trust architecture

with high performance cryptographic processing and

manufacturing protection

Low-cost board designs

The LS1012A package is engineered to support low-cost,

4-layer board designs to minimize system costs