DA9211 datasheet(32/74 Pages) DIALOG

32 / 74 page

DA9211 and DA9212

Datasheet

Company confidential

Data sheet

Version <3.0>

<07-Jan-2015>

CFR0011-120-00 Rev 3

32 of 74

DC-DC Buck Converter

13.1

DA9211 is a four-phase 12 A high efficiency synchronous step-down DVC regulator, operating at a

high frequency of typically 3 MHz. It supplies an output voltage of typically 1.0 V for a CPU rail,

configurable in the range 0.3

– 1.57 V, with high accuracy in steps of 10 mV.

DA9212 contains two buck converters, Buck A and Buck B, each capable of delivering 6 A

To improve the accuracy of the delivered voltage, each buck converter is able to support a differential

sensing of the configured voltage directly at the point of load via dedicated positive and negative

sense pins.

Both Buck A and Buck B have two voltage registers each. One defines the normal output voltage,

while the other offers an alternative retention voltage. In this way different application power modes

can easily be supported. The voltage selection can be operated either via GPI or via control interface

to guarantee the maximum flexibility according to the specific host processor status in the

application.

When a buck is enabled, its output voltage is monitored and a power-good signal indicates that the

buck output voltage has reached a level higher than the VTH(PG) threshold. The power-good is lost

when the voltage drops below VTH(PG) - VHYS(PG), which is the level at which the signal is de-asserted.

The power good signalling should not be used in conjunction with fast start up rates, configured in

BUCKx_UP_CTRL register fields and can be individually masked during DVC transitions using the

PGA_DVC_MASK and PGB_DVC_MASK bits. For each of the buck converters the status of the

power-good indicator can be read back via I2C from the PWRGOOD_A and PWRGOOD_B status

bits. It can be also individually assigned to either GPIO2 or GPIO3 using BUCKA_PG_SEL and

BUCKB_PG_SEL. For correct functionality, the GPIO ports need to be configured as output. An I2C

write in GPIOx_MODE can overwrite the internal configuration so that a new update will be

automatically done only when the internal power-good indicator changes status.

The buck converters are capable of supporting DVC transitions that occur:

● When the active and selected A-voltage or B-voltage is updated to a new target value.

● When the voltage selection is changed from the A-voltage to the B-voltage (or B-voltage to the

A-voltage) using VBUCKA_SEL and VBUCKB_SEL.

The DVC controller operates in Pulse Width Modulation (PWM) mode with synchronous rectification.

When the host processor changes the output voltage, the voltage transition of each buck converter

can be individually signalled with a READY signal routed to either GPIO2 or GPIO3. The port has to

be configured as GPO and selected for the functionality via READYA_CONF or READYB_CONF. In

contrast to the power-good signal, the READY only informs the host processor about the completion

of the digital DVC ramp without confirming that the target voltage has actually been reached.

The slew rate of the DVC transition is individually programmed for each buck converter at 10mV per

(4, 2, 1 or 0.5 µs) via control bit SLEW_RATE_A and SLEW_RATE_B.

The typical supply current is in the order of 8 mA per phase (quiescent current and charge/discharge

current) and drops to <1 µA when the buck is turned off.

When the buck is disabled, a pull-down resistor (typically

150 Ω) for each phase is activated

depending of the value stored in register bits BUCKA_PD_DIS and BUCKB_PD_DIS. Phases

disabled using PHASE_SEL_A and PHASE_SEL_B will not have any pull-down. The pull-down

resistor is always disabled at all phases when DA9211 and DA9212 are OFF.

Switching Frequency

13.1.1

The switching frequency is chosen to be high enough to allow the use of a small 0.47 µH inductor

(see a complete list of coils in the Application Information section (see section 15). The buck

DA9211 数据表(PDF) 32 Page - Dialog Semiconductor

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