8761CY

www.icst.com/products/hiperclocks.html

REV. C SEPTEMBER 7, 2004

10

Integrated

Circuit

Systems, Inc.

ICS8761

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS8761 provides sepa-

rate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required.

Figure 1 illustrates how

a 10

Ω resistor along with a 10µF and a .01µF bypass

capacitor should be connected to each V

10

Ω

V

DDA

10

µF

.01

µF

3.3V

.01

µF

V

DD

C2

SPARE

XTAL2

XTAL1

X1

18pF Parallel Cry stal

C1

SPARE

The ICS8761 crystal interface is shown in

Figure 2. While layout

the PC Board, it is recommended to provide C1 and C2 spare

footprints for frequency fine tuning. For an 18pF parallel reso-

nant crystal, the C1 and C2 are expected to be ~10pF and ~5pF

respectively.