DP7221 datasheet(2/16 Pages) COPAL

2 / 16 page

DP7221

Doc. No. MD-2113 Rev. K

Characteristics subject to change without notice

PIN DESCRIPTION

Pin (SOIC)

Name

Function

1RW0

Wiper Terminal for Potentiometer 0

2RL0

Low Reference Terminal for Potentiometer 0

3RH0

High Reference Terminal for Potentiometer 0

Device Address, LSB

Device Address

6RW1

Wiper Terminal for Potentiometer 1

7RL1

Low Reference Terminal for Potentiometer 1

8RH1

High Reference Terminal for Potentiometer 1

SDA

Serial Data Input/Output

GND

Ground

No Connect

SCL

Bus Serial Clock

Device Address

No Connect

VCC

Supply Voltage

PIN DESCRIPTION

SCL: Serial Clock

The DP7221 serial clock input pin is used to clock

all data transfers into or out of the device.

SDA: Serial Data

The DP7221 bidirectional serial data pin is used to

transfer data into and out of the device. The SDA pin

is an open drain output and can be wire-Or'd with

the other open drain or open collector outputs.

A0, A1, A2, A3: Device Address Inputs

These

inputs

set

the

device

address

when

addressing multiple devices. A total of sixteen

devices can be addressed on a single bus. A match

in the slave address must be made with the address

input in order to initiate communication with the

DP7221.

RH, RL: Resistor End Points

The two sets of RH and RL pins are equivalent to the

terminal connections on a mechanical potentiometer.

RW: Wiper

The two RW pins are equivalent to the wiper terminal

of a mechanical potentiometer.

DEVICE OPERATION

The DP7221 is two resistor arrays integrated with 2-

wire serial interface logic, two 6-bit wiper control

registers and eight 6-bit, non-volatile memory data

registers. Each resistor array contains 63 separate

resistive elements connected in series. The physical

ends of each array are equivalent to the fixed terminals

of a mechanical potentiometer (RH and RL). RH and RL

are symmetrical and may be interchanged. The tap

positions between and at the ends of the series resis–

tors are connected to the output wiper terminals (RW)by

a CMOS transistor switch. Only one tap point for each

potentiometer is connected to its wiper terminal at a

time and is determined by the value of the wiper control

registers or the non-volatile memory data registers via

the 2-wire bus. Additional instructions allow data to be

transferred between the wiper control registers and

each

respective

potentiometer's

non-volatile

data

registers. Also, the device can be instructed to operate

in an "increment/decrement" mode.

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