LPC2292 datasheet(26/40 Pages) PHILIPS

26 / 40 page

Philips Semiconductors

LPC2292/LPC2294

16/32-bit ARM microcontrollers with external memory interface

Preliminary data

Rev. 01 — 05 February 2004

26 of 40

9397 750 12748

6.21.5

Memory Mapping Control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x00000000. Vectors may be mapped to the bottom of the

on-chip Flash memory, or to the on-chip static RAM. This allows code running in

different memory spaces to have control of the interrupts.

6.21.6

Power Control

The LPC2292/LPC2294 support two reduced power modes: Idle mode and

Power-down mode. In Idle mode, execution of instructions is suspended until either a

Reset or interrupt occurs. Peripheral functions continue operation during Idle mode

and may generate interrupts to cause the processor to resume execution. Idle mode

eliminates power used by the processor itself, memory systems and related

controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal

clocks. The processor state and registers, peripheral registers, and internal SRAM

values are preserved throughout Power-down mode and the logic levels of chip

output pins remain static. The Power-down mode can be terminated and normal

operation resumed by either a Reset or certain speciﬁc interrupts that are able to

function without clocks. Since all dynamic operation of the chip is suspended,

Power-down mode reduces chip power consumption to nearly zero.

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings.

6.21.7

VPB bus

The VPB Divider determines the relationship between the processor clock (cclk) and

the clock used by peripheral devices (PCLK). The VPB Divider serves two purposes.

The ﬁrst is that the VPB bus cannot operate at the highest speeds of the CPU. In

order to compensate for this, the VPB bus may be slowed down to one half or one

fourth of the processor clock rate. The default condition at reset is for the VPB bus to

run at one quarter of the CPU clock. The second purpose of the VPB Divider is to

allow power savings when an application does not require any peripherals to run at

the full processor rate. Because the VPB Divider is connected to the PLL output, the

PLL remains active (if it was running) during Idle mode.

6.22 Emulation and debugging

The LPC2292/LPC2294 support emulation and debugging via a JTAG serial port. A

trace port allows tracing program execution. Debugging and trace functions are

multiplexed only with GPIOs on Port 1. This means that all communication, timer and

interface peripherals residing on Port 0 are available during the development and

debugging phase as they are when the application is run in the embedded system

itself.

6.22.1

Embedded ICE™

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging

of the target system requires a host computer running the debugger software and an

EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the

Remote Debug Protocol commands to the JTAG data needed to access the ARM

core.

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