Data Sheet

9

Rev. 1.0 2015-11-02

TLS810B1LDV50

General Product Characteristics

4.3

Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go

to www.jedec.org.

Table 3

Thermal Resistance TLS810B1 in PG-TSON-10 Package

Parameter

Symbol

Values

Unit

Note or

Test Condition

Number

Min.

Typ.

Max.

Package Version

1) Not subject to production test, specified by design

–

13

–

K/W

–

P_4.3.1

Junction to Ambient

–60

–

K/W

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm

Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

P_4.3.2

Junction to Ambient

–

184

–

K/W

1s0p board, footprint

P_4.3.3

Junction to Ambient

–

75

–

K/W

P_4.3.4

Junction to Ambient

–

64

–

K/W

P_4.3.5