MSC1200 datasheet(21/60 Pages) TI

21 / 60 page

MSC1200

SBAS289E

www.ti.com

FIGURE 12. External Crystal Connection.

XIN

XOUT

NOTE: Refer to the crystal manufacturer's specification

for C

1 and C2 values.

FIGURE 13. External Clock Connection.

XIN

External Clock

FIGURE 14. PLL Connection.

XOUT

XIN

32.768kHz

NOTE: Typical configuration is shown.

clock, or external oscillator. If an external clock is detected at

startup, then the CPU will begin execution in ECM after

startup. If an external clock is not detected at startup, then

the device will revert to the mode shown in Table II.

PLL

In Phase Lock Loop (PLL) mode (HCR2, CLKSEL = 101 or

HCR2, CLKSEL = 100), the CPU can execute from an

external 32.768 kHz crystal. This mode enables the use of a

phase-lock loop (PLL) circuit that synthesizes the selected

clock frequencies (PLL LF mode or PLL HF mode). If an

external clock is detected at startup, then the CPU will begin

execution in PLL mode after startup. If an external clock is

not detected at startup, then the device will revert to the

mode shown in Table II. The status of the PLL can be

determined by first writing the PLLLOCK bit (enable) and

then reading the PLLLOCK status bit in the PLLH SFR.

The frequency of the PLL is preloaded with default trimmed

values. However, the PLL frequency can be fine-tuned by

writing to the PLLDIV1 and PLLDIV0 SFRs. The equation for

the PLL frequency is:

PLL Frequency = ((PLLDIV9:PLLDIV0) + 1) • fOSC

where fOSC = 32.768kHz.

The default value for PLL LF mode is automatically loaded

into the PLLDIV SFR. For PLL HF mode, the user must load

PLLDIV with the appropriate value (0383H).

For different connections to external clocks, see Figures 12,

13, and 14.

SPI

The MSC1200 implements a basic SPI interface which in-

cludes the hardware for simple serial data transfers. Figure 15

shows a block digram of the SPI. The peripheral supports

master and slave mode, full duplex data transfers, both clock

polarities, both clock phases, bit order, and slave select.

FIGURE 15. SPI/I2C Block Diagram.

SPI /I2C

Data Write

SPICON

I2CCON

I2C

Stretch

Control

Counter

Start/Stop

Detect

SPI /I2C

Data Read

Pad Control

DOUT

P1.2

P1.4

P3.6

P1.3

Logic

DOUT

TX_CLK

RX_CLK

SCK/SCL

CNT_CLK

CNT INT

I2C INT

DIN

CLKS

(refer to PASEL, SFR F2

SCK

DIN

MSC1200 数据表(PDF) 21 Page - Texas Instruments

MSC1200 数据表(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载