2003 Dec 17

7

Philips Semiconductors

Product specification

32 kHz watch circuit with programmable

adaptive motor pulse

PCA2000; PCA2001

Time calibration

The quartz crystal oscillator has an integrated capacitance

of 5.2 pF, which is lower than the specified capacitance

oscillator frequency is typically 60 ppm higher than

32.768 kHz. This positive frequency offset is compensated

by removing the appropriate number of 8192 Hz pulses in

the divider chain (maximum 127 pulses), every

1 or 2 minutes. The time correction is given in Table 1.

After measuring the effective oscillator frequency, the

number of correction pulses must be calculated and stored

together with the calibration period in the OTP memory

(see Section “Programming the memory cells”).

The oscillator frequency can be measured at pad RESET,

where a square wave signal with the frequency of

is provided.

This frequency shows a jitter every minute or every two

minutes, depending on the programmed calibration period,

which originates from the time calibration.

Details on how to measure the oscillator frequency and the

programmed inhibit time are given in Section

“Measurement of oscillator frequency and inhibit time”.

Reset

At pin RESET an output signal with a frequency of

= 32 Hz is provided.

opens all four (P1, N1, P2 and N2) driver switches (see

mode. In this mode the motor output frequency is 32 Hz,

which can be used to test the mechanical function of the

watch.

After releasing the pad RESET, the motor starts exactly

one second later with the smallest duty cycle and with the

opposite polarity to the last pulse before stopping.

The debounce time for the RESET function is between

31 and 62 ms.

Programming possibilities

The programming data is stored in OTP cells (EPROM

cells). At delivery, all memory cells are in state 0. The cells

can be programmed to the state 1, but then there is no

more set back to state 0.

The programming data is organized in an array of three

8-bit words: word A contains the time calibration, and

words B and C contain the setting for the monitor pulses

(see Table 2).

1

1024

-------------

f

osc

×

1

1024

-------------

f

osc

×

Table 1

Time calibration

Table 2

Words and bits

CALIBRATION PERIOD

CORRECTION PER STEP (n = 1)

CORRECTION PER STEP (n = 127)

ppm

seconds per day

ppm

seconds per day

1 minute

2.03

0.176

258

22.3

2 minutes

1.017

0.088

129

11.15

WORD

BIT

1

2

3

4

5678

A

number of 8192 Hz pulses to be removed

calibration

period

B

lowest stage: duty cycle

number of driving stages

highest stage:

duty cycle and

stretching

factory test bit

C

pulse width

maximum time delay between positive

and negative detection pulses

EOL

voltage

factory test

bit