REG104FA-2.7SLASH500 datasheet(9/22 Pages) TI

9 / 22 page

REG104

SBVS025G

100

0.1

0.01

0.001

Enable Voltage

FIGURE 4. Enable Pin Current versus Applied Voltage.

The Enable Pin Current versus Applied Voltage relationship

is shown in Figure 4. When the Enable pin is connected to

VIN greater than 10V, a series resistor may be used to limit

the current.

FIGURE 5. Block Diagram.

FIGURE 6. Output Noise versus Noise Reduction Capacitor.

Since the value of VREF is 1.295V, this relationship reduces to:

RMS

OUT

•

Connecting a capacitor, CNR, from the Noise-Reduction (NR)

pin to ground can reduce the output noise voltage. Adding

CNR, as shown in Figure 5, forms a low-pass filter for the

voltage reference. For CNR = 10nF, the total noise in the

10Hz to 100kHz bandwidth is reduced by approximately

a factor of 3.5. This noise reduction effect is shown in

Figure 6.

Over Current

Over Temp

Protection

REF

(1.295V)

Low Noise

Charge Pump

DMOS

Output

NOTE: R

1 and R2 are internal

on fixed output versions.

OUT

Adj

(Adjustable

Versions)

(fixed output

versions only)

Enable

REG104

(optional)

0.001

0.01

0.1

NR (µF)

OUT = 0

OUT = 10µF

REG104-3.3

OUTPUT NOISE

A precision band-gap reference is used for the internal

reference voltage, VREF, for the REG104. This reference is

the dominant noise source within the REG104. It generates

approximately 45

µV

RMS in the 10Hz to 100kHz bandwidth at

the reference output. The regulator control loop gains up the

reference noise, so that the noise voltage of the regulator is

approximately given by:

RMS

OUT

REF

=µ

•

The REG104 adjustable version does not have the noise-

reduction pin available, however, the adjust pin is the

summing junction of the error amplifier. A capacitor, CFB,

REG104FA-2.7/500 数据表(PDF) 9 Page - Texas Instruments

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