Copyright 2000 National Semiconductor Corp.

2

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1.0 CONNECTION DIAGRAM

Order Number SC14425XVJG (Standard version)

X=silicon revision

See NS Package Number VJG100A

Note 1:

All digital outputs can sink/source 2 mA unless otherwise specified. All digital inputs are Schmitt trigger types. After reset all I/Os are set to input

and all pull-up or pull-down resistors are enabled unless otherwise specified.

PU = Pull-up resistor enabled, PD = Pull-down resistor enabled, I = input

A-I, B-I = In Boot mode A or B input and pull-up or pull-down resistor disabled,

A-PD, B-PU = In Boot mode A, Pull-down resistor enabled. In Boot mode B, pull-up resistor enabled.

Note 2:

Reset state of address and WRn, RDn pins:

Hi-Z/1 means Hi-Z if RSTn is LOW, if RSTn goes HIGH is takes 32 SCLK cycles = 25 usec before these pin drives a ‘1’.

Note 3:

5 Volt protection pads: type *P may NOT be connected to an external pull down resistor

DAB0

AD0

AD1

AD2

AD3

P1[6]

HOLDn

RSTn

Xtal1

DAC

AVS2

AVD2

LRS2+

LRS2-

VREF2-

MIC2-

AGND

MIC2+

VREF2+

CAP2+

CAP2-

N.C.

CAP

SCLK

VDD

VSS

PD7

PD6

PD5

PD4

PD3

PD2

PD1

DAC2

MEN1n

SO

SK

VDDRF

RDI

CMPREF

RSSI

AVD

AVS

TDO

RFCLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

SC14425

MI INTn7

ACSn INTn6

P1[7]

N.C.

N.C.

N.C.

DAB 1

DAB2