SN74LVC2T45

DUALBIT DUALSUPPLY BUS TRANSCEIVER

WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3STATE OUTPUTS

SCES516E − DECEMBER 2003 − REVISED MAY 2004

1

POST OFFICE BOX 655303

NanoStar

 and NanoFree Packages

Each Port to Operate Over the Full 1.65-V to

5.5-V Power-Supply Range

Is at GND, Both Ports Are in the

High-Impedance State

Operation

− 420 Mbps (3.3-V to 5-V Translation)

− 210 Mbps (Translate to 3.3 V)

− 140 Mbps (Translate to 2.5 V)

− 75 Mbps (Translate to 1.8 V)

JESD 78, Class II

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

DCT OR DCU PACKAGE

(TOP VIEW)

1

2

3

4

8

7

6

5

A1

A2

GND

B1

B2

DIR

4

3

2

1

5

6

7

8

GND

A2

A1

DIR

B2

B1

YEP OR YZP PACKAGE

(BOTTOM VIEW)

description/ordering information

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is

translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVC2T45 is designed for asynchronous communication between data buses. The device transmits

data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the

direction-control (DIR) input.

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING‡

NanoStar

 − WCSP (DSBGA)

0.23-mm Large Bump − YEP

Reel of 3000

SN74LVC2T45YEPR

_ _ _TB_

−40 C to 85 C

NanoFree

 − WCSP (DSBGA)

0.23-mm Large Bump − YZP (Pb-free)

Reel of 3000

SN74LVC2T45YZPR

_ _ _TB_

−40

°C to 85°C

SSOP − DCT

Reel of 3000

SN74LVC2T45DCTR

CT2_ _ _

SSOP − DCT

Reel of 250

SN74LVC2T45DCTT

CT2_ _ _

VSSOP − DCU

Reel of 3000

SN74LVC2T45DCUR

CT2_

VSSOP − DCU

Reel of 250

SN74LVC2T45DCUT

CT2_

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

‡ DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.

DCU: The actual top-side marking has one additional character that designates the assembly/test site.

YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one

following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition

(1 = SnPb,

Copyright

 2004, Texas Instruments Incorporated

NanoStar and NanoFree are trademarks of Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.