STLC2410B

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GENERAL SPECIFICATION

6.1 SYSTEM CLOCK

The STLC2410B works with a single clock provided on the XIN pin. The value of this external clock should

be 13MHz ±20ppm (overall).

6.1.1 SLOW CLOCK

The slow clock is used by the baseband as reference clock during the low power modes. Compared to the

13MHz clock, the slow clock only requires an accuracy of ±250ppm (overall).

Several options are foreseen in order to adjust the STLC2410B behaviour according to the features of the

radio used:

– if the system clock (e.g. 13MHz) is not provided at all times (power consumption saving) and no slow

clock is provided by the system, a 32 kHz crystal must be used by the STLC2410B (default mode).

– if the system clock (e.g. 13MHz) is not provided at all times (power consumption saving) and the system

provides a slow clock at 32kHz or 3.2kHz, this signal in simply connected to the STLC2410B

(lpo_clk_p).

– if the system clock (e.g. 13MHz) is provided at all times, the STLC2410B generates from the 13MHz

reference clock an internal 32kHz clock. This mode is not an optimized mode for power consumption.

6.2 BOOT PROCEDURE

The boot code instructions are the first that ARM7TDMI executes after an HW reset. All the internal de-

vice's registers are set to their default value.

There are 2 types of boot:

– external flash boot.

When boot pin is set to `1` (connected to VDD), the STLC2410B boots on its external memory which is

normally a flash memory.

– UART download boot from ROM.

When boot pin is set to `0` (connected to GND), the STLC2410B boots on its internal ROM (needed to

download the new firmware).

When booting on the internal ROM, the STLC2410B will monitor the UART interface for approximately 1.4

second. If there is no request for code downloading during this period, the ROM jumps to external flash.

6.3 CLOCK DETECTION

The STLC2410B has a automatic slow clock frequency detection (32kHz, 3.2kHz or none).

6.4 MASTER RESET

When the device's reset is held active (NRESET is low), all two uart txd pins (UART1_TXD and

UART2_TXD) are driven low. When the NRESET returns high, the device starts to boot.

Remark: The device should be held in active reset for minimum 20ms in order to guarantee a complete

reset of the device.

6.5 INTERRUPTS/WAKE-UP

The external pins int1 and int2, and up to 8 GPIOs can be used both as external interrupt source and as

wake-up source. In addition the chip can be woken-up by USB or Uart Rx.