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STV7620M 数据表(PDF) 13 Page - STMicroelectronics |
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STV7620M 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 17 page ![]() STV7620M 13/17 11 AC TIMING CHARACTERISTICS (Vcc = 5V, Vpp = 70 V, Vssp = 0V, Vsssub = 0V, Vsslog = 0V, Tamb = 25°C, FCLK = 40 MHz,) (Vilmax = 0.2Vcc, Vihmin = 0.8Vcc) Note 8: one output among 96, loading capacitor CL = 50 pF, other outputs at low level Symbol Parameter Min. Typ Max Unit tPHL1 tPLH1 Delay of power output change after CLK transition - high to low - low to high - - 35 30 100 100 ns ns tPHL2 tPLH2 Delay of power output change after STB transition - high to low - low to high - - - 95 95 ns ns tPHL3 tPLH3 Delay of power output change after BLK, POC transition - high to low - low to high - 25 20 90 90 ns ns tR OUT Power output rise time (Note 8) 50 - 200 ns tF OUT Power output fall time (Note 8) 50 - 200 ns tS Width of the falling edge smooth shape (not tested) - 30 - ns tR DAT Logic data output rise time (CL = 10pF) - 9 20 ns tF DAT Logic data output fall time (CL = 10pF) - 5 12 ns tPHL4 tPLH4 Delay of logic data output change after CLK transition - high to low - low to high - - 12 13 25 25 ns ns |
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