 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
TAS5036IPFC 数据表(PDF) 33 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TAS5036IPFC 数据表(HTML) 33 Page - Texas Instruments |
|
|
33 / 49 page  System Initialization 28 SLES044B—November 2002 TAS5036 4 System Initialization Reset is used during system initialization to hold the TAS5036 inactive while power (VDD), the master clock (MCLK_IN), the device control, and the data signals become stable. The recommended initialization sequence is to hold RESET low for 24 MCLK_IN cycles after VDD has reached 3 V and the other control signals (MUTE, PDN, M_S, ERR_RCVRY,, DBSPD, and CS0) are stable. MCLK VDD 3 V 24 MCLK_IN Cycles RESET Figure 4–1. RESET During System Initialization The serial data interface format is then set through the serial data interface control register using the serial control interface. At this point the TAS5036 is fully operational. However, the operation of the TAS5036 can be tailored as desired to meet specific operating requirements by adjusting the following: • Automute delay register • DC-Offset control registers • Interchannel delay registers |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
