VPC323XD datasheet(41/78 Pages) MICRONAS

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ADVANCE INFORMATION

VPC 323xD, VPC 324xD

Micronas

h’14e

Status of automatic standard recognition

bit[0]

error of the vertical standard (neither 50 nor 60 Hz)

bit[1]

detected standard is disabled

bit[2]

search active

bit[3]

search terminated, but failed

bit[3:0]

0000 all ok

0001 search not started, because vwin error detected

(no input or SECAM L)

0010 search not started, because detected vert. standard

not enabled

x1x0 search started and still active

1x00 search failed (found standard not correct)

1x10 search failed, (detected color standard not enabled)

ASR_STATUS

VWINERR

DISABLED

BUSY

FAILED

h’21

Input select:

writing to this register will also initialize the standard

bit[1:0]

luma selector

VIN3

VIN2

VIN1

VIN4

bit[2]

chroma selector

0/1

VIN1/CIN

bit[4:3]

IF compensation

off

6 dB/Okt

12 dB/Okt

10 dB/MHz only for SECAM

bit[6:5]

chroma bandwidth selector

narrow

normal

broad

wide

bit[7]

0/1

adaptive/fixed SECAM notch filter

bit[8]

0/1

enable luma lowpass filter

bit[10:9]

hpll speed

no change

terrestrial

vcr

mixed

bit[11]

status bit, write 0, this bit is set to 1 to indicate

operation complete.

INSEL

VIS

CIS

IFC

CBW

FNTCH

LOWP

HPLLMD

h’22

picture start position: This register sets the start point of active video

and can be used e.g. for panning. The setting is updated when ‘sdt’

ten.

0SFIF

h’23

luma/chroma delay adjust. The setting is updated when ‘sdt’ register

is updated.

bit[5:0]

reserved, set to zero

bit[11:6]

luma delay in clocks, allowed range is +1 ... –7

0LDLY

h’29

helper delay register (PAL+ mode only)

bit[11:0]

delay adjust for helper lines adjustable from

–96...96, 1 step corresponds to 1/32 clock

HLP_DLY

FP Sub-

address

Function

Default

Name

VPC323XD 数据表(PDF) 41 Page - Micronas

VPC323XD 数据表(HTML) 41 Page - Micronas

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