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AD1835AS 数据表(PDF) 4 Page - Analog Devices

部件名 AD1835AS
功能描述  2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
PDF  23 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD1835AS 数据表(HTML) 4 Page - Analog Devices

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PRELIMINARY TECHNICAL DATA
–4–
AD1835–SPECIFICATIONS
TIMING
Parameter
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
tMH
MCLK High
15
ns
tML
MCLK Low
15
ns
tPDR
PD/RST Low
20
ns
SPI PORT
tCCH
CCLK High
40
ns
tCCL
CCLK Low
40
ns
tCCP
CCLK Period
80
ns
tCDS
CDATA Setup
10
ns
To CCLK Rising
tCDH
CDATA Hold
10
ns
From CCLK Rising
tCLS
CLATCH Setup
10
ns
To CCLK Rising
tCLH
CLATCH Hold
10
ns
From CCLK Rising
tCOE
COUT Enable
15
ns
From CLATCH Falling
tCOD
COUT Delay
20
ns
From CCLK Falling
tCOTS
COUT Three-State
25
ns
From CLATCH Rising
DAC SERIAL PORT
Normal Mode (Slave)
tDBH
DBCLK High
60
ns
tDBL
DBCLK Low
60
ns
fDB
DBCLK Frequency
64
fS
tDLS
DLRCLK Setup
10
ns
To DBCLK Rising
tDLH
DLRCLK Hold
10
ns
From DBCLK Rising
tDDS
DSDATA Setup
10
ns
To DBCLK Rising
tDDH
DSDATA Hold
10
ns
From DBCLK Rising
Packed 256 Modes (Slave)
tDBH
DBCLK High
15
ns
tDBL
DBCLK Low
15
ns
fDB
DBCLK Frequency
256
fS
tDLS
DLRCLK Setup
10
ns
To DBCLK Rising
tDLH
DLRCLK Hold
5
ns
From DBCLK Rising
tDDS
DSDATA Setup
10
ns
To DBCLK Rising
tDDH
DSDATA Hold
10
ns
From DBCLK Rising
ADC SERIAL PORT
Normal Mode (Master)
tABD
ABCLK Delay
25
ns
From MCLK Rising Edge
tALD
ALRCLK Delay Low
5
ns
From ABCLK Falling Edge
tABDD
ASDATA Delay
10
ns
From ABCLK Falling Edge
Normal Mode (Slave)
tABH
ABCLK High
60
ns
tABL
ABCLK Low
60
ns
fAB
ABCLK Frequency
64
fS
tALS
ALRCLK Setup
5
ns
To ABCLK Rising
tALH
ALRCLK Hold
15
ns
From ABCLK Rising
Packed 256 Mode (Master)
tPABD
ABCLK Delay
20
ns
From MCLK Rising Edge
tPALD
LRCLK Delay
5
ns
From ABCLK Falling Edge
tPABDD
ASDATA Delay
10
ns
From ABCLK Falling Edge



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