Data Sheet

5

Version1.0

2016-06-15

TLE4955C

Confidential

Functional Description

1.2

Block Diagram

Figure 3

Block Diagram

core for peak detection and offset calculation will be executed. The offset is fed back into the speed signal path

with a digital to analog converter for offset correction. The adaptive hysteresis comparator compares the

speed signal to the hysteresis value. During uncalibrated mode, the output of the speed pulse is triggered in

the digital core by exceeding a certain threshold.

The direction signal is calculated out of the three Hall signals. The direction signal is amplified, filtered, and

digitized. In the digital core the direction and the vibration detection information is determined and the data

protocol is issued. The direction information is converted to a current modulated signal.

Supply

Comparator

LPF

dir

calc

Offset DAC

LPF

2 (right)

1 (left)

3 (center )

Amplifier Speed Path

ESD

Supply Voltage Generation

Bandgap

Oscillator

Offset

Calculation

multiplexed

ADC

Output

Protocol

Tracking

ADC

Algorithm

Direction

Detection

Adaptive

Hysteresis

Comparator

Vibration

Detection

Current

Modulator

GND