CS8405A

DS469PP4

21

8.7

Interrupt 2 Status (8h) (Read Only)

For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register

was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the register.

Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true.

Status bits that are masked off in the associated mask register will always be “0” in this register. This register defaults

to 00h.

EFTU - E to F U-buffer transfer interrupt. (Block Mode only)

The source of this bit is true during the E to F buffer transfer in the U bit buffer management process.

8.8

Interrupt 1 Mask (9h)

The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error is unmasked,

meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked,

meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre-

sponding bits in Interrupt 1 register. This register defaults to 00h.

8.9

Interrupt 1 Mode MSB (Ah) and Interrupt 1 Mode LSB(Bh)

The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to

set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin be-

comes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active

on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the in-

terrupt condition. Be aware that the active level(Actice High or Low) only depends on the INT[1:0] bits. These regis-

ters default to 00.

00 - Rising edge active

01 - Falling edge active

10 - Level active

11 - Reserved

8.10

Interrupt 2 Mask (Ch)

The bits of this register serve as a mask for the Interrupt 2 register. If a mask bit is set to 1, the error is unmasked,

meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked,

meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre-

sponding bits in Interrupt 2 register. This register defaults to 00h.

7

6

5

43210

00

0

0

0

EFTU

0

0

7

6

5

43210

TSLIPM

0

0

000

EFTCM

0

7

6

5

43210

TSLIP1

0

0

0

0

0

EFTC1

0

TSLIP0

0

0

0

0

0

EFTC0

0

7

6

5

43210

00

0

0

0

EFTUM

0

0