DIT4192

6

SBOS229B

www.ti.com

MASTER CLOCK

The DIT4192 requires a master clock for operation. This

clock must be supplied at the MCLK input (pin 6). The

maximum master clock frequency that may be supplied to

MCLK is 25MHz. Table I shows master clock rates for

common input sampling frequencies.

RESET AND POWER-DOWN

OPERATION

used to force a reset sequence. When the DIT4192 is first

enable normal operation. For software mode, the reset se-

quence will force all internal registers to their default settings.

In addition, the reset sequence will force all channel status

bits to 0 in Software mode.

TX– (pin 17) and TX+ (pin 18), are forced to ground.

low until the rising edge of the SYNC clock is detected at

pin 12. Once this occurs, the TX– and TX+ outputs will

become active and be driven by the output of the AES-3

encoder.

In Software mode, the DIT4192 also includes software reset

PDN, are both active high.

AUDIO SERIAL PORT

The audio serial port is a 3-wire interface used to connect the

DIT4192 to an audio source, such as an A/D converter or

DSP. The port supports sampling frequencies up to 192kHz.

The port signals include SDATA (pin 13), SYNC (pin 12), and

SCLK (pin 11). The SDATA pin is the serial data input for the

port. The SCLK pin may be either an input or output, and is

used to clock serial data into the port. The SYNC pin may be

either an input or output, and provides the frame synchroni-

FIGURE 3. AES-3 Frame Format.

MASTER CLOCK FREQUENCY (MHz)

SAMPLING

FREQUENCY (kHz)

22.05

n/a

5.6448

8.4672

11.2896

24

n/a

6.144

9.216

12.288

32

n/a

8.192

12.288

16.384

44.1

n/a

11.2896

16.9344

22.5792

48

n/a

12.288

18.432

24.576

88.2

n/a

22.5792

n/a

n/a

96

n/a

24.576

n/a

n/a

176.4

22.5792

n/a

n/a

n/a

192

24.576

n/a

n/a

n/a

TABLE I. Master Clock Frequencies for Common Sampling

Rates.

CONTROL BITS OR INPUT PINS

CLK1

CLK0

MASTER CLOCK (MCLK) SELECTION

0

0

0

1

1

0

1

1

TABLE II. Master Clock Rate Selection for Software and

Hardware Modes.

For Software mode, the master clock frequency selection is

programmed using the CLK0 and CLK1 bits in Control

CLK1 (pin 4) inputs are used to select the master clock

frequency. Table II shows the available MCLK frequency

selections.

Channel A

X

XY

Y

Z

Channel A

Channel A

Channel B

Channel B

Channel B

Frame 191

Frame 0

Frame 1

Start of Channel Status Block

One Sub-Frame

Preamble

Aux Data

LSB

MSB

V U C P

27 28 29 30 31

Audio Data

Validity Data

User Data

Parity Bit

Channel Status Data

Bits: 0

3 4

7 8