PCM4202

SBAS290B − JULY 2003 − SEPTEMBER 2004

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13

ANALOG INPUTS

The PCM4202 includes two channels of A/D conversion,

each with its own pair of differential voltage input pins. The

correspond to the Right channel input. The average input

impedance of each input pin is 3k

Ω.

Each analog input pair accepts a full-scale input voltage of

power supply by more than 300mV. Refer to the

Applications Information section of this datasheet for an

example input buffer circuit.

VOLTAGE REFERENCES AND COMMON MODE

BIAS VOLTAGE OUTPUTS

The PCM4202 includes two on-chip voltage references,

reference

outputs

for

Left

and

Right

channels,

respectively. De-coupling capacitors are connected

between each of these pins and the corresponding

recommended to have at least a 0.1

µF X7R ceramic chip

capacitor connected in parallel with a 33

µF low ESR

tantalum chip capacitor for de-coupling purposes. The

external circuitry, because they are not buffered. Use the

circuitry, as described in the following paragraphs.

Refer to the Applications Information section of this

datasheet for the recommended voltage reference pin

connections.

The PCM4202 analog inputs are internally biased to

channels, respectively. These outputs provide a level

shifting voltage for biasing external input buffer circuitry.

buffered, the output current is limited to a few hundred

µA.

It is recommended to connect these pins to external nodes

with greater than 1M

Ω impedance, or to buffer the outputs

with a voltage follower circuit when driving multiple

external or low impedance nodes.

Refer to the Applications Information section of this

datasheet for an example input buffer circuit that utilizes

the common-mode bias voltage outputs.

SYSTEM CLOCK INPUT

The PCM4202 requires an external system clock, from

which the modulator oversampling and digital sub-system

clocks are derived. The system clock is applied at the

SCKI input (pin 18). The frequency of the system clock is

dependent upon the desired PCM output sampling

frequency or DSD data rate, along with the sampling mode

selection. Table 1 shows the corresponding system clock

frequencies for common output sampling and data rates,

along with the corresponding sampling modes. Timing

requirements for the system clock are shown in Figure 2.

Table 1. System Clock Frequencies for Common Output Sampling and Data Rates

SAMPLING FREQUENCY, fS

SYSTEM CLOCK FREQUENCY (MHz)

SAMPLING MODE

SAMPLING FREQUENCY, fS

(kHz)

128fS

192fS

256fS

384fS

512fS

768fS

Single Rate

32

n/a

n/a

8.192

12.288

16.384

24.576

Single Rate

44.1

n/a

n/a

11.2896

16.9344

22.5792

33.8688

Single Rate

48

n/a

n/a

12.288

18.432

24.576

36.864

Dual Rate

88.2

n/a

n/a

22.5792

33.8688

n/a

n/a

Dual Rate

96

n/a

n/a

24.576

36.864

n/a

n/a

Quad Rate

176.4

22.5792

33.8688

n/a

n/a

n/a

n/a

Quad Rate

192

24.576

36.864

n/a

n/a

n/a

n/a

DSD Output

128fS Data (Single Rate)

n/a

n/a

11.2896

16.9344

22.5792

33.8688

DSD Output

64fS Data (Dual Rate)

n/a

n/a

11.2896

16.9344

n/a

n/a