Symbol

Parameter

Limit

Units

Min

Max

10

Output Data Valid

55

ns

11

Output Data Hold Time

15

ns

12

CS Inactive Time

10

ns

Note: Data guaranteed by design.

I

I

In I

need a pull-up resistor according to I

V

I

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can

only be changed when CLK is LOW.

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I

START and STOP bits classify the beginning and the end of the I

transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH

while SCL is HIGH. The I

condition and free after STOP condition. During data transmission, I

START and repeated START conditions are equivalent, function-wise.

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TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data

has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter

releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock

pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been

received.

After the START condition, the I

is a data direction bit (R/W). The LP3936 address is 36h. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ.

The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register.

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