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OMAP3530ECBB 数据表(PDF) 47 Page - Texas Instruments

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部件名 OMAP3530ECBB
功能描述  OMAP3530 and OMAP3525 Applications Processors
PDF  265 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECBB 数据表(HTML) 47 Page - Texas Instruments

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OMAP3530, OMAP3525
www.ti.com
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
Table 2-2. Ball Characteristics (CBC Pkg.)(1)
BALL
BALL
BUFFER
PULLUP
BALL
BALL TOP
PIN NAME
RESET REL.
MODE [4]
TYPE [5]
RESET
RESET REL.
POWER [9]
HYS [10]
STRENG TH
/DOWN
IO CELL [13]
BOTTOM [1]
[2]
[3]
MODE [8]
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
AE16
NA
cam_d0
0
I
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_99
4
I
safe_mode
7
-
AE15
NA
cam_d1
0
I
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_100
4
I
safe_mode
7
-
AD17
NA
gpio_112
4
I
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
safe_mode
7
-
AE18
NA
gpio_114
4
I
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
safe_mode
7
-
AD16
NA
gpio_113
4
I
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
safe_mode
7
-
AE17
NA
gpio_115
4
I
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
safe_mode
7
-
NA
G20
sdrc_a0
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
K20
sdrc_a1
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
J20
sdrc_a2
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
J21
sdrc_a3
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
U21
sdrc_a4
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
R20
sdrc_a5
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
M21
sdrc_a6
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
M20
sdrc_a7
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
N20
sdrc_a8
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
K21
sdrc_a9
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
Y16
sdrc_a10
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
N21
sdrc_a11
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
R21
sdrc_a12
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
AA15
sdrc_a13
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
Y12
sdrc_a14
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
AA18
sdrc_ba0
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
V20
sdrc_ba1
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
Y15
sdrc_cke0
0
O
H
1
7
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
safe_mode
7
NA
Y13
sdrc_cke1
0
O
H
1
7
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
safe_mode
7
NA
A12
sdrc_clk
0
IO
L
0
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
D1
sdrc_d0
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
G1
sdrc_d1
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
G2
sdrc_d2
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
E1
sdrc_d3
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
D2
sdrc_d4
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
E2
sdrc_d5
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
(1)
NA in this table stands for Not Applicable.
(2)
The drive strength is programmable vs the capacity load: load range = [2 pF to 6 pF] per default or [6 pF to 12 pF] according to the
selected mode.
Copyright © 2008–2013, Texas Instruments Incorporated
TERMINAL DESCRIPTION
47
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Product Folder Links: OMAP3530 OMAP3525



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