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OMAP3530ECBBA 数据表(PDF) 54 Page - Texas Instruments

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部件名 OMAP3530ECBBA
功能描述  OMAP3530 and OMAP3525 Applications Processors
PDF  265 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECBBA 数据表(HTML) 54 Page - Texas Instruments

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OMAP3530, OMAP3525
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.)(1) (continued)
BALL
BALL
BUFFER
PULLUP
BALL
BALL TOP
PIN NAME
RESET REL.
MODE [4]
TYPE [5]
RESET
RESET REL.
POWER [9]
HYS [10]
STRENG TH
/DOWN
IO CELL [13]
BOTTOM [1]
[2]
[3]
MODE [8]
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
gpio_191
4
IO
safe_mode
7
-
V19
NA
hsusb0_dir
0
I
L
L
7
vdds
Yes
4
(7)
PU100/
LVCMOS
PD100
gpio_122
4
IO
safe_mode
7
-
W18
NA
hsusb0_nxt
0
I
L
L
7
vdds
Yes
4
(7)
PU100/
LVCMOS
PD100
gpio_124
4
IO
safe_mode
7
-
U20
NA
hsusb0_stp
0
O
H
H
7
vdds
Yes
4
(7)
PU100/
LVCMOS
PD100
gpio_121
4
IO
safe_mode
7
-
U15
NA
jtag_ntrst
0
I
L
L
0
vdds
Yes
NA
PU100/
LVCMOS
PD100
W13
NA
jtag_rtck
0
O
L
0
0
vdds
Yes
4
PU100/
LVCMOS
PD100
V14
NA
jtag_tck
0
I
L
L
0
vdds
Yes
NA
PU100/
LVCMOS
PD100
U16
NA
jtag_tdi
0
I
H
H
0
vdds
Yes
NA
PU100/
LVCMOS
PD100
Y13
NA
jtag_tdo
0
O
L
Z
0
vdds
Yes
4
PU100/
LVCMOS
PD100
V15
NA
jtag_tms_tms
0
IO
H
H
0
vdds
Yes
4
PU100/
LVCMOS
c
PD100
N19
NA
mmc1_clk
0
O
L
L
7
vdds_mmc1
Yes
8
PU100/
LVCMOS
PD100
gpio_120
4
IO
safe_mode
7
-
L18
NA
mmc1_cmd
0
IO
L
L
7
vdds_mmc1
Yes
8
PU100/
LVCMOS
PD100
gpio_121
4
IO
safe_mode
7
-
M19
NA
mmc1_dat0
0
IO
L
L
7
vdds_mmc1
Yes
8
PU100/
LVCMOS
PD100
gpio_122
4
IO
safe_mode
7
-
M18
NA
mmc1_dat1
0
IO
L
L
7
vdds_mmc1
Yes
8
PU100/
LVCMOS
PD100
gpio_123
4
IO
safe_mode
7
-
K18
NA
mmc1_dat2
0
IO
L
L
7
vdds_mmc1
Yes
8
PU100/
LVCMOS
PD100
gpio_124
4
IO
safe_mode
7
-
N20
NA
mmc1_dat3
0
IO
L
L
7
vdds_mmc1
Yes
8
PU100/
LVCMOS
PD100
gpio_125
4
IO
safe_mode
7
-
M20
NA
mmc1_dat4
0
IO
L
L
7
vdds_mmc1a
No
8
PU/PD
(8)
LVCMOS
gpio_126
4
IO
safe_mode
7
-
P17
NA
mmc1_dat5
0
IO
L
L
7
vdds_mmc1a
No
8
PU/PD
(8)
LVCMOS
gpio_127
4
IO
safe_mode
7
-
P18
NA
mmc1_dat6
0
IO
L
L
7
vdds_mmc1a
No
8
PU/PD
(8)
LVCMOS
gpio_128
4
IO
safe_mode
7
-
(8)
The PU nominal drive strength of this IO cell is equal to 25 mA @ 1.8 V and 41.6 mA @ 3.0 V. The PD nominal drive strength of this IO
cell is equal to 1 mA @ 1.8 V and 1.66 mA @ 3.0 V.
54
TERMINAL DESCRIPTION
Copyright © 2008–2013, Texas Instruments Incorporated
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Product Folder Links: OMAP3530 OMAP3525



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