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OMAP3530ECBC 数据表(PDF) 192 Page - Texas Instruments |
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OMAP3530ECBC 数据表(HTML) 192 Page - Texas Instruments |
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192 / 265 page  OMAP3530, OMAP3525 SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 www.ti.com Table 6-31. ISP Timing Conditions – 8-bit Packed SYNC – Interlaced Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2.5 ns tF Input signal fall time 2.5 ns Output Conditions CLOAD Output load capacitance 8.6 pF Table 6-32. ISP Timing Requirements – 8-bit Packed SYNC – Interlaced Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX ISP3 tc(pclk) Cycle time(2), cam_pclk period 7.7 15.4 ns ISP4 tW(pclkH) Typical pulse duration, cam_pclk high 0.5*P(3) 0.5*P(3) ns ISP4 tW(pclkL) Typical pulse duration, cam_pclk low 0.5*P(3) 0.5*P(3) ns tdc(pclk) Duty cycle error, cam_pclk 385 769 ps tj(pclk) Cycle jitter(4), cam_pclk 83 167 ps ISP5 tsu(dV-pclkH) Setup time, cam_d[11:0] valid before cam_pclk 1.08 2.27 ns rising edge ISP6 th(pclkH-dV) Hold time, cam_d[11:0] valid after cam_pclk rising 1.08 2.27 ns edge ISP7 tsu(dV-vsH) Setup time, cam_vs valid before cam_pclk rising 1.08 2.27 ns edge ISP8 th(pclkH-vsV) Hold time, cam_vs valid after cam_pclk rising edge 1.08 2.27 ns ISP9 tsu(dV-hsH) Setup time, cam_hs valid before cam_pclk rising 1.08 2.27 ns edge ISP10 th(pclkH-hsV) Hold time, cam_hs valid after cam_pclk rising edge 1.08 2.27 ns ISP11 tsu(dV-hsH) Setup time, cam_wen valid before cam_pclk rising 1.08 2.27 ns edge ISP12 th(pclkH-hsV) Hold time, cam_wen valid after cam_pclk rising edge 1.08 2.27 ns ISP13 tsu(dV-fldH) Setup time, cam_fld valid before cam_pclk rising 1.08 2.27 ns edge ISP14 th(pclkH-fldV) Hold time, cam_fld valid after cam_pclk rising edge 1.08 2.27 ns (1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified. (2) Related with the input maximum frequency supported by the ISP module. (3) P = cam_lclk period in ns. (4) Maximum cycle jitter supported by cam_pclk input clock. Table 6-33. ISP Switching Characteristics – 8-bit Packed SYNC – Interlaced Mode NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX ISP16 tc(xclk) Cycle time(1), cam_xclk period 4.6 4.6 ns ISP2 tW(xclkH) Typical pulse duration, cam_xclk high 0.5*PO(2) 0.5*PO(2) ns ISP2 tW(xclkL) Typical pulse duration, cam_xclk low 0.5*PO(2) 0.5*PO(2) ns tdc(xclk) Duty cycle error, cam_xclk 231 231 ps tj(xclk) Jitter standard deviation(3), cam_xclk 67 67 ps tR(xclk) Rise time, cam_xclk 0.93 0.93 ns tF(xclk) Fall time, cam_xclk 0.93 0.93 ns (1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module. Warning: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98] (2) PO = cam_xclk period in ns. (3) The jitter probability density can be approximated by a Gaussian function. 192 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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