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OMAP3530ECBC 数据表(PDF) 62 Page - Texas Instruments

部件名 OMAP3530ECBC
功能描述  OMAP3530 and OMAP3525 Applications Processors
PDF  265 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECBC 数据表(HTML) 62 Page - Texas Instruments

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OMAP3530, OMAP3525
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.)(1) (continued)
BALL
BALL
BUFFER
PULLUP
BALL
BALL TOP
PIN NAME
RESET REL.
MODE [4]
TYPE [5]
RESET
RESET REL.
POWER [9]
HYS [10]
STRENG TH
/DOWN
IO CELL [13]
BOTTOM [1]
[2]
[3]
MODE [8]
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
safe_mode
7
-
H25
NA
dss_data7
0
IO
L
L
7
vdds
Yes
8
PU100/
LVCMOS
PD100
uart1_rx
2
I
gpio_77
4
IO
hw_dbg15
5
O
safe_mode
7
-
H26
NA
dss_data8
0
IO
L
L
7
vdds
Yes
8
PU100/
LVCMOS
PD100
gpio_78
4
IO
hw_dbg16
5
O
safe_mode
7
-
J26
NA
dss_data9
0
IO
L
L
7
vdds
Yes
8
PU100/
LVCMOS
PD100
gpio_79
4
IO
hw_dbg17
5
O
safe_mode
7
-
L25
NA
dss_data16
0
IO
L
L
7
vdds
Yes
8
PU100/
LVCMOS
PD100
gpio_86
4
IO
safe_mode
7
-
L26
NA
dss_data17
0
IO
L
L
7
vdds
Yes
8
PU100/
LVCMOS
PD100
gpio_87
4
IO
safe_mode
7
-
M24
NA
dss_data18
0
IO
L
L
7
vdds
Yes
8
PU100/
LVCMOS
PD100
mcspi3_clk
2
IO
dss_data0
3
IO
gpio_88
4
IO
safe_mode
7
-
M26
NA
dss_data19
0
IO
L
L
7
vdds
Yes
8
PU100/
LVCMOS
PD100
mcspi3_simo
2
IO
dss_data1
3
IO
gpio_89
4
IO
safe_mode
7
-
N24
NA
dss_data21
0
O
L
L
7
vdds
Yes
8
PU100/
LVCMOS
PD100
mcspi3_cs0
2
IO
dss_data3
3
IO
gpio_91
4
IO
safe_mode
7
-
K24
NA
dss_hsync
0
O
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_67
4
IO
hw_dbg13
5
O
safe_mode
7
-
M25
NA
dss_vsync
0
O
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_68
4
IO
safe_mode
7
-
R8
NA
mcspi1_cs1
0
O
H
H
7
vdds
Yes
4
(17)
PU100/
LVCMOS
PD100
mmc3_cmd
3
IO
gpio_175
4
IO
safe_mode
7
-
(17) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in
the above table.
62
TERMINAL DESCRIPTION
Copyright © 2008–2013, Texas Instruments Incorporated
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Product Folder Links: OMAP3530 OMAP3525



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