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OMAP3530ECBC 数据表(PDF) 212 Page - Texas Instruments |
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OMAP3530ECBC 数据表(HTML) 212 Page - Texas Instruments |
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212 / 265 page  mcspix_cs0(EPOL=1) mcspix_clk(POL=0) mcspix_clk(POL=1) mcspix_simo mcspix_somi mcspix_cs0(EPOL=1) mcspix_clk(POL=0) mcspix_clk(POL=1) mcspix_simo mcspix_somi Bitn-1 Bitn-2 Bitn-3 Bitn-4 Bit0 Bitn-1 Bitn-2 Bitn-3 Bitn-4 Bit0 Bitn-1 Bitn-2 Bitn-3 Bit1 Bit0 Bitn-1 Bitn-2 Bitn-3 Bit1 Bit0 SS4 SS5 SS6 SS3 SS1 SS0 SS2 SS1 SS0 SS4 SS5 SS3 SS1 SS0 SS1 SS0 SS2 SS6 SS7 Mode0&2 Mode1&3 030-076 OMAP3530, OMAP3525 SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 www.ti.com Figure 6-41. McSPI Interface – Transmit and Receive in Slave Mode(1) (2) (1) The active clock edge (rising or falling) on which mcspi_somi is driven and mcspi_simo data is latched is software configurable with the bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL. (2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL In mcspix, x is equal to 1, 2, 3, or 4. 6.6.2.2 McSPI in Master Mode Table 6-73 and Table 6-74 assume testing over the recommended operating conditions (see Figure 6-42). Table 6-73. McSPI1, 2, and 4 Interface Timing Requirements – Master Mode(1) (2) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX SM2 tsu(SOMIV-CLKAE) Setup time, mcspix_somi valid before mcspix_clk 1.1 1.5 ns active edge SM3 th(SOMIV-CLKAE) Hold time, mcspix_somi valid after mcspix_clk active 1.9 2.8 ns edge (1) The input timing requirements are given by considering a rise time and a fall time of 4 ns. (2) In mcspix, x is equal to 1, 2, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4. 212 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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