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OMAP3530ECBC 数据表(PDF) 145 Page - Texas Instruments |
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OMAP3530ECBC 数据表(HTML) 145 Page - Texas Instruments |
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145 / 265 page  OMAP3530, OMAP3525 www.ti.com SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 and Table 4-16 show the DPLL1 and DPLL2 clock frequency ranges. Note: The DPLL1 and DPLL2 clock frequency ranges depend on the VDD1 (vdd_mpu _iva) operating point. Table 4-15. DPLL1 Clock Frequency Ranges Clock Signal Description Max Unit OPP6(1) 720 MHz OPP5 600 MHz OPP4 550 MHz ARM_CLK DPLL1 output clock. OPP3 500 MHz OPP2 250 MHz OPP1(2) 125 MHz (1) OPP6 frequency range is only supported on high-speed grade OMAP3530/25 devices. (2) Cannot boot in OPP1. If OPP1 is desired, boot in higher OPP then switch to OPP1. Table 4-16. DPLL2 Clock Frequency Ranges Clock Signal Description Max Unit OPP6(1) 520 MHz OPP5 430 MHz OPP4 400 MHz Generated from DPLL2 output IVA2_CLK clock. OPP3 360 MHz OPP2 180 MHz OPP1(2) 90 MHz (1) OPP6 frequency range is only supported on high-speed grade OMAP3530/25 devices. (2) Cannot boot in OPP1. If OPP1 is desired, boot in higher OPP then switch to OPP1. Table 4-17 through Table 4-19 show the DPLL3 clock frequency ranges. Note: The DPLL3 clock frequency ranges depend on the VDD2 (vdd_core) operating point and the L3 clock speed configuration. Table 4-17. DPLL3 Clock Frequency Ranges, VDD2 OPP3 Config 1 Config 2 (166 MHz) (133 MHz) Unit Clock Signal Description Min Max Min Max Output of clock manager (CM), generated CM: CORE_CLK - 332 - 266 MHz directly from DPLL3. Output of clock manager (CM), generated CM: L3_ICLK - 166 - 133 MHz using DPLL3. Output of clock manager (CM), generated CM: L4_ICLK - 83 - 66.5 MHz using CM L3_ICLK and divider. SGX SGX input clock, taken from CM CORE_CLK. - 110.67 - 88.67 MHz SDRC SDRC input clock, taken from CM L3_ICLK. - 166 - 133 MHz GPMC GPMC input clock, taken from CM L3_ICLK. - 83 - 66.5 MHz Table 4-18. DPLL3 Clock Frequency Ranges, VDD2 OPP2 Config 1 Config 2 (83 MHz) (100 MHz) Unit Clock Signal Description Min Max Min Max Output of clock manager (CM), generated CM: CORE_CLK - 166 - 200 MHz directly from DPLL3. Output of clock manager (CM), generated using CM: L3_ICLK - 83 - 100 MHz DPLL3. Copyright © 2008–2013, Texas Instruments Incorporated CLOCK SPECIFICATIONS 145 Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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