PL620-88/-89

Low Phase Noise XO (9.5-65MHz Output)

Rev 4/28/09 Page 2

PACKAGE PIN ASSIGNMENT

Name

Pin#

Description

VDD

1

Power Supply.

XIN

2

Crystal input. See Crystal Specification on page 3.

XOUT

3

Crystal output. See Crystal Specification on page 3.

DNC

4, 7, 15, 16

Do Not Connect.

S2

5

Output Divide by Two selector pin. See the OUTPUT DIVIDE BY TWO

SELECTOR table on page 1.

OE

6

Output Enable input. See OUTPUT ENABLE LOGIC table on page 1.

GND

8, 9

Ground.

GNDBUF

10

Ground for output buffer circuitry.

Q

11

LVPECL or LVDS output.

VDDBUF

12

Power supply for output buffer circuitry.

QBAR

13

Complementary LVPECL or LVDS output.

GNDBUF

14

Ground for output buffer circuitry.

ELECTRICAL SPECIFICAT IONS

1. Absolute Maximum Ratings

PARAMETERS

SYMBOL

MIN

MAX

UNITS

Supply Voltage

4.6

V

Input Voltage, dc

-0.5

V

Output Voltage, dc

-0.5

V

Storage Temperature

-65

150

C

Ambient Operating Temperature

-40

85

C

Junction Temperature

125

C

Lead Temperature (soldering, 10s)

260

C

ESD Protection, Human Body Model

2

kV

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for exten ded periods may cause permanent damage to the

device and affect product reliability. These conditions represent a stress rating only, and functional operations of the dev ice at these or any other

conditions above the operational limits noted in this specification is not implied.