PL600-27T

Low Power 3 Output XO

LAYOUT RECOMMENDATIONS

The following guidelines are to assist you with a pe rformance optimized PCB design:

Signal Integrity and Termination

Considerations

- Keep traces short!

- Trace = Inductor. With a capacitive load this equals

ringing!

- Long trace = Transmission Line. Without proper ter-

mination this will cause reflections ( looks like ringing ).

- Design long traces (> 1 inch) as “striplines” or

“microstrips” with defined impedance.

- Match trace at one side to avoid reflections bouncing

back and forth.

Decoupling and Power Supply

Considerations

- Place decoupling capacitors as close as possible to

the VDD pin(s) to limit noise from the power supply

- Multiple VDD pins should be decoupled separately

for best performance.

- Addition of a ferrite bead in series with VDD can

help prevent noise from other board sources

- Value of decoupling capacitor is frequency de-

pendant. Typical values to use are 0.1

F for de-

signs using frequencies < 50MHz and 0.01

F for

designs using frequencies > 50MHz.

Crystal Tuning Circuit

Series and parallel capacitors used to fine tune the crystal load to the circuit load.

CST – Series Capacitor, used to lower circuit load to match crystal load. Raises frequency

offset. This can be eliminated by using a crystal with a Cload of equal or greater value than the

oscillator.

CPT – Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers

frequency offset.

Crystal

XIN

1

8

XOUT

Cpt

Cpt

Cst

Typical LVCMOS termination

Place Series Resistor as close as possible to LVCMOS output

LVCMOS Output Buffer

( Typical buffer impedance 20



To LVCMOS Input

Series Resistor

Use value to match output

buffer impedance to 50



trace. Typical value 30



50

 line