| 数据搜索系统,热门电子元器件搜索 |
|
PL502-37QC-R 数据表(PDF) 5 Page - Micrel Semiconductor |
|
|
|||||||||||||||||||||||||||||
PL502-37QC-R 数据表(HTML) 5 Page - Micrel Semiconductor |
|
5 / 10 page ![]() PL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise ICs Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/15/13 Page 5 5. Jitter Specifications PARAMETERS CONDITIONS FREQUENCY MIN. TYP. MAX. UNITS Period jitter RMS With capacitive decoupling between VDD and GND. Over 10,000 cycles. 19.44MHz 2.2 ps 77.76MHz 4.5 155.52MHz 4.5 622.08MHz 5.0 Period jitter Peak-to-Peak With capacitive decoupling between VDD and GND. Over 10,000 cycles. 19.44MHz 17 ps 77.76MHz 25 155.52MHz 27 622.08MHz 35 Integrated jitter RMS Integrated 12kHz to 20MHz 155.52MHz 2.5 4 ps 622.08MHz 2.5 4 6. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS Phase Noise relative to carrier (typical) 19.44MHz -80 -108 -132 -142 -150 dBc/Hz 77.76MHz -72 -103 -122 -130 -125 155.52MHz -65 -95 -120 -125 -121 622.08MHz -55 -85 -109 -115 -110 Note: Phase Noise measured at VCON = 0V 7. LVCMOS Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Output drive current IOH VOH= VDD-0.4V, VDD=3.3V 10 mA IOL VOL = 0.4V, VDD = 3.3V 10 mA Output Clock Rise/Fall Time 0.3V ~ 3.0V with 15 pF load 2.4 ns |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |