PL502-35/-37/-38/-39

750kHz

– 800MHz Low Phase Noise Multiplier VCXO

Universal Low Phase Noise ICs

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/15/13 Page 1

FEATURES

 Selectable 750kHz to 800MHz range

 Low phase noise output (@ 10kHz frequency off-

set, -142dBc/Hz for 19.44MHz, -125dBc/Hz for

155.52MHz, -115dBc/Hz for 622.08MHz)

 LVCMOS (PL502-37), LVPECL (PL502-35 and

PL502-38) or LVDS (PL502-39) output

 12MHz to 25MHz crystal input

 No external load capacitor or varicap required.

 Output Enable selector

 Wide pull range (±200 ppm)

 Selectable /16 to x32 frequency divider/multiplier

 3.3V operation

 Available in 16-Pin TSSOP or 16-pin 3x3mm QFN

GREEN/RoHS compliant packages

DESCRIPTION

The PL502-35 (LVPECL with inverted OE), PL502-37

(LVCMOS), PL502-38 (LVPECL), and PL502-39

(LVDS) are high performance and low phase noise

VCXO IC chips. They provide phase noise perfor-

mance as low as –125dBc at 10kHz offset (at

155MHz), by multiplying the input crystal frequency up

to 32x. The wide pull range (±200 ppm) and very low

jitter make them ideal for a wide range of applications,

including SONET/SDH and FEC. They accept funda-

mental parallel resonant mode crystals from 12MHz to

25MHz.

BLOCK DIAGRAM

PIN CONFIGURATION

(Top View)

^: Internal pull-up

*: On 3x3 package, PL502-35/-38 do not have SEL0 available: Pin 10

is VDD, pin 11 is GND. However, PL502-37/-39 have SEL0 (pin 10),

and pin11 is VDD. See pin assignment table for details.

OUTPUT ENABLE LOGICAL LEVELS

Part #

OE

State

PL502-38

0 (Default) Output enabled

1

Tri-state

PL502-35

PL502-37

PL502-39

0

Tri-state

1 (Default) Output enabled

OE input: Logical states defined by LVPECL levels for PL502-38

Logical states defined by LVCMOS levels for PL502-37/-39

1

2

3

4

5

6

7

8

VDD

9

1

0

1

1

1

2

1

3

1

4

1

5

1

6

XIN

XOUT

SEL3^

SEL2^

OE

VCON

GND

SEL0^

SEL1^

GND

CLKC

VDD

CLKT

GND

GND

TSSOP-16L

PL502-3x

1

2

3

4

12

11

10

9

13

14

15

16

8

7

6

5

SEL3^

XOUT

SEL2^

OE

VDD

CLKT

CLKC

GND

QFN-16L

XIN

XOUT

OE

CLKT

PL502-3x

VCON

CLKC

PLL by-pass

SEL[3:0]

PLL

(Phase

Locked

Loop)

Oscillator

Amplifier

w/

integrated

varicaps