PL500-17

Low Phase Noise VCXO (17MHz to 36MHz)

FEATURES

 VCXO output for the 17MHz to 36MHz range

 Low phase noise (-130dBc @ 10kHz offset at

35.328MHz)

 LVCMOS output with OE tri-state control

 17 to 36MHz fundamental crystal input

 Integrated high linearity variable capacitors

 8mA drive capability at TTL output

 ±150 ppm pull range, max 5% (typ.) linearity

 Low jitter (RMS): 2.5ps period jitter

 2.5 to 3.3V operation

 Available in 8-Pin SOP, 6-pin SOT23 GREEN/

RoHS compliant packages, or Die

DESCRIPTION

The PL500-17 is a low cost, high performance and

low phase noise VCXO for the 17 to 36MHz range,

providing less than -130dBc at 10kHz offset at

35.328MHz. The very low jitter (2.5 ps RMS period

jitter) makes this chip ideal for applications requiring

voltage controlled frequency sources. Input crystal

can range from 17 to 36MHz (fundamental resonant

mode).

BLOCK DIAGRAM

PIN CONFIGURATION

1

2

3

4

5

6

7

8

XIN

VDD*

VCON

GND

XOUT

VDD*

CLK

OE^

1

2

3

4

5

6

XOUT

GND

CLK

XIN

VCON

VDD

SOP-8L

SOT23-6L

^: Denotes internal Pull-up

*: Only one VDD pin needs to be connected

OE

XIN

XOUT

VCON

Varicap

Xtal

Osc

CLK