(Preliminary)

PL123E-09

Low Skew Zero Delay Buffer

FEATURES

 Frequency Range 10MHz to 220MHz

 Zero input - output delay.

 Low Output to Output Skew

 Optional Drive Strength:

Standard (8mA) PL123E-09

High (12mA)

PL123E-09H

 2.5V or 3.3V, ±10% operation.

 Available in 16-Pin SOP or TSSOP packages

DESCRIPTION

The PL123E-09 (-09H for High Drive) is a high perfor-

mance, low skew, low jitter zero delay buffer d esigned

to distribute high speed clocks. It has two low-skew

output banks, of 4 outputs each, that are synchronized

with the input. Control of the two banks of outputs is

achieved by using the S1 and S2 inputs as shown in

the Selector Definition table on page 2.

The synchronization is established via CLKOUT feed

back to the input of the PLL. Since the skew between

the input and output is less than

100ps, the device

acts as a zero delay buffer. The input output propaga-

tion delay can be advanced or delayed by adjusting the

load on the CLKOUT pin.

These parts are not intended for 5V input-tolerant ap-

plications.

BLOCK DIAGRAM

PLL

REF

CLKOUT

CLKA1

CLKA2

CLKA3

CLKA4

Selector

Inputs

Mux

CLKB1

CLKB2

CLKB3

CLKB4

S1

S2

1

REF

CLKA1

CLKA2

VDD

CLKOUT

CLKA4

CLKA3

VDD

GND

CLKB4

CLKB3

S1

10

11

12

13

14

15

16

9

8

7

6

5

4

3

2

S2

CLKB2

CLKB1

GND