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PL123E-05HSC-R 数据表(PDF) 1 Page - Micrel Semiconductor |
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PL123E-05HSC-R 数据表(HTML) 1 Page - Micrel Semiconductor |
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1 / 10 page ![]() (Preliminary) PL123E-05 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 1 FEATURES Frequency Range 10MHz to 220MHz Zero input - output delay. Low output-to-output skew. Optional Drive Strength: Standard (8mA) PL123E-05 High (12mA) PL123E-05H 2.5V or 3.3V, ±10% operation. Available in 8-pin SOP packaging. DESCRIPTION The PL123E-05 (-05H for High Drive) is a high perfor- mance, low skew, low jitter zero delay buffer d esigned to distribute high speed clocks. It has five low-skew outputs that are synchronized with the input. The syn- chronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than 100ps, the device acts as a zero delay buffer. The input output propagation delay can be advanced or delayed by adjusting the load on the CLKOUT pin. These parts are not intended for 5V input-tolerant ap- plications. PIN CONFIGURATION SOP-8L BLOCK DIAGRAM 1 2 3 4 REF 5 6 7 8 CLK2 CLK1 GND CLKOUT CLK4 VDD CLK3 PLL REF CLKOUT CLK1 CLK2 CLK3 CLK4 |
类似零件编号 - PL123E-05HSC-R |
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类似说明 - PL123E-05HSC-R |
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