PL123-05/-09

Low Skew Zero Delay Buffer

Page 5

SWITCHING CHARACTERISTICS

[5]

Parameter Name

Test Conditions

Min.

Typ.

Max.

Unit

Output Frequency

30-pF load

10

–

100

MHz

10-pF load

10

–

134

MHz

40

50

60

%

45

50

55

%

Measured between 0.8V and 2.0V

–

–

2.5

ns

Measured between 0.8V and 2.0V

–

–

1.5

ns

Measured between 0.8V and 2.0V

–

–

2.5

ns

Measured between 0.8V and 2.0V

–

–

1.5

ns

Output to Output Skew

All outputs equally loaded

–

–

250

ps

Delay, REF Rising Edge to

Measured at VDD/2

–

0

±350

ps

Delay, REF Rising Edge to

Measured at VDD/2. Measured in PLL bypass

mode, PL123-09 only.

1

5

8.5

ns

Measured at VDD/2 on the CLKOUT pin

–

0

700

ps

Measured between 0.8V and 2.0V using Test

Circuit #2

1

–

–

V/ns

Measured at 66.67 MHz, loaded outputs

–

75

200

ps

Stable power supply, valid clock presented on

REF pin

–

–

1

ms

Notes:

4. Parameter is guaranteed by design and characterization. Not 100% tested in production.

5. All parameters are specified with loaded outputs.